S-818A55AMC-BHJT2G 데이터 시트보기 (PDF) - Seiko Instruments Inc

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S-818A55AMC-BHJT2G

LOW DROPOUT CMOS VOLTAGE REGULATOR

Seiko Instruments Inc 

LOW DROPOUT CMOS VOLTAGE REGULATOR

S-818 Series

Rev.2.1_00

„ Precautions

• Wiring patterns for the VIN pin, VOUT pin and GND pin should be designed so that the impedance is low.

When mounting an output capacitor (CL) or an input capacitor (CIN), the distance from the capacitor to the

VOUT pin and to the VSS pin should be as short as possible.

• Note that output voltage may increase when a voltage regulator is used at low load current (Less than

10 µA).

• To prevent oscillation, the external components should be used under the following conditions:

Input capacitor (CIN):

0.47µF or more

Output capacitor (CL):

2 µF or more

Equivalent series resistance (ESR): 10 Ω or less

Input series resistance (RIN):

10 Ω or less

• The voltage regulator may oscillate when the impedance of the power supply is high and the input

capacitor is small or not connected.

• The application condition for input voltage and load current should not exceed the package power

dissipation.

• In determining output current, attention should be paid to the output current value specified and footnote *5

in Table 5 in the “„ Electrical Characteristics”.

• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in

electrostatic protection circuit.

• SII claims no responsibility for any and all disputes arising out of or in connection with any infringement by

products including this IC of patents owned by a third party.

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Seiko Instruments Inc.

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