S-8253AAA-T8T1GZ 데이터 시트보기 (PDF) - Seiko Instruments Inc
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S-8253AAA-T8T1GZ Datasheet PDF : 32 Pages
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BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Rev.3.7_00
7. Delay Circuit
The following detection delay times are determined by dividing a clock of approximately 3.57 kHz by the counter.
(Example) Oscillator clock cycle (TCLK) :
Overcharge detection delay time (tCU) :
Overdischarge detection delay time (tDL) :
Overcurrent detection delay time 1 (tIOV1) :
Overcurrent detection delay time 2 (tIOV2) :
280 µs
1.15 s
144 ms
9 ms
4.5 ms
Remark The overcurrent detection delay time 2 (tIOV2) and overcurrent detection delay time 3 (tIOV3) start when the
overcurrent detection voltage 1 (VIOV1) is detected. As soon as the overcurrent detection voltage 2 (VIOV2) or
overcurrent detection voltage 3 (VIOV3) is detected over the detection delay time for overcurrent 2 (tIOV2) or
overcurrent 3 (tIOV3) after the detection of overcurrent 1 (VIOV1), the S-8253A/B turns the discharging control
FET off within tIOV2 or tIOV3 of each detection.
VDD
DOP pin voltage
VSS
VMP pin voltage
VDD
VIOV1
VIOV2
VIOV3
VSS
Overcurrent detection
delay time 2 (tIOV2)
Figure 10
tD
0 ≤ tD ≤ tIOV2
Time
Time
8. CTL Pin
The S-8253A/B Series has a control pin for charge / discharge control and shortening the test time. The levels, “L”, “H”,
and “M”, of the voltage input to the CTL pin determine the status of the S-8253A/B Series: normal operation, charge /
discharge inhibition, or test time shortening. The CTL pin takes precedence over the battery protection circuit. During
normal use, short the CTL pin and VSS pin.
Table 10 Conditions Set by CTL Pin
CTL Pin Potential
Status of IC
Open
Charge / discharge inhibited status
High (VCTL ≥ VCTLH)
Middle (VCTLL < VCTL < VCTLH)
Charge / discharge inhibited status
Delay time-shortening status *1
Low (VCTLL ≥ VCTL)
Normal status
*1. In this status, delay times are shortened in 1 / 60 to 1 / 30 scale.
*2. The pin status is controlled by the voltage detection circuit.
COP Pin
High-Z
High-Z
(*2)
(*2)
DOP Pin
VDD
VDD
(*2)
(*2)
Caution 1. If the potential of the CTL pin is middle, overcurrent detection voltage 1 (VIOV1) does not operate.
2. If you use the middle potential of the CTL pin, contact SII marketing department.
3. Please note unexpected behavior might occur when electrical potential difference between the
CTL pin (“L” level) and VSS is generated through the external filter (RVSS and CVSS) as a result of
input voltage fluctuations.
18
Seiko Instruments Inc.
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