S3C72H8 데이터 시트보기 (PDF) - Samsung

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S3C72H8

The S3C72H8 single-chip CMOS microcontroller has been designed for very high performance using Samsung's state-of-the-art 4-bit product development approach, SAM47

Samsung 

S3C72H8/P72H8

S3P72H8 OTP

Main Chip

Pin Name

P0.1

P0.2

TEST

RESET

VDD / VSS

Table 18-1. Pin Descriptions Used to Read/Write the EPROM

Pin Name

SDAT

SCLK

VPP (TEST)

RESET

VDD / VSS

Pin No.

7

8

13

16

9/10

During Programming

I/O

Function

I/O Serial data pin. Output port when reading and

input port when writing can be assigned as

Input/push-pull output port respectively.

I/O Serial clock pin. Input only pin.

I

Power supply pin for EPROM cell writing

(indicates that OTP enters into the writing

mode). When 12.5 V is applied, OTP is in

writing mode and when 5 V is applied, OTP is in

reading mode. (Option)

I

Chip initialization

I

Logic power supply pin. VDD should be tied to

+ 5 V during programming.

Table 18-2. Comparison of S3P72H8 and S3C72H8 Features

Characteristic

Program Memory

Operating Voltage (VDD)

OTP Programming Mode

Pin Configuration

EPROM Programmability

S3P72H8

8 K-byte EPROM

1.8 V to 5.5 V

VDD = 5 V, VPP (TEST) = 12.5 V

64 QFP

User Program 1 time

S3C72H8

8 K-byte mask ROM

1.8 V to 5.5 V

–

64 QFP

Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the VPP (TEST) pin of the S3P72H8, the EPROM programming mode is entered. The

operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 18-3 below.

Table 18-3. Operating Mode Selection Criteria

VDD

VPP

(TEST)

5V

5V

12.5V

12.5V

12.5V

REG/

MEM

0

0

0

1

Address

(A15-A0)

0000H

0000H

0000H

0E3FH

R/W

Mode

1

EPROM read

0

EPROM program

1

EPROM verify

0

EPROM read protection

NOTE: "0" means low level; "1" means high level.

18-3

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