S5L9284 데이터 시트보기 (PDF) - Samsung

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S5L9284

DIGITAL SIGNAL PROCESSOR

Samsung 

S5L9284D

DIGITAL SIGNAL PROCESSOR

DIGITAL PLL BLOCK

This device contains analog PLL and digital PLL together, in order to obtain the stable channel clock for

demodulating the EFM signal.

The block diagram of digital PLL is as follows.

X - Tal

Voltage

Controlled

Low

Pass

Filter

Voltage

Controlled

Oscillator

I/N

Divider

Digital

PLL

Figure 20. The Application Diagram of Digital PLL

/PBCK

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