SAA7120H 데이터 시트보기 (PDF) - Philips Electronics

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SAA7120H

Video Input Processor VIP

Philips Electronics 

Philips Semiconductors

Digital video encoder

Product specification

SAA7120H; SAA7121H

7.8 I2C-bus format

Table 4 I2C-bus address; see Table 5

S SLAVE ADDRESS ACK SUBADDRESS

ACK DATA 0 ACK --------

DATA n ACK P

Table 5 Explanation of Table 4

PART

S

SLAVE ADDRESS

ACK

SUBADDRESS; note 2

DATA

--------

P

DESCRIPTION

START condition

1000 100X or 1000 110X; note 1

acknowledge, generated by the slave

subaddress byte

data byte

continued data bytes and ACKs

STOP condition

Notes

1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read; no subaddressing with read.

2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.

7.9 Slave receiver

Table 6 Subaddresses 26H and 27H

DATA BYTE

WSS

WSSON

LOGIC

LEVEL

−

0

1

DESCRIPTION

wide screen signalling bits

3 to 0 = aspect ratio

7 to 4 = enhanced services

10 to 8 = subtitles

13 to 11 = reserved

wide screen signalling output is disabled; default after reset

wide screen signalling output is enabled

Table 7 Subaddresses 28H and 29H

DATA BYTE

BS

BE

DECCOL

DECFIS

LOGIC

LEVEL

−

−

0

1

0

1

DESCRIPTION

REMARKS

starting point of burst in clock cycles

ending point of burst in clock cycles

disable colour detection bit of RTCI input

enable colour detection bit of RTCI input

field sequence as FISE in subaddress 61

field sequence as FISE bit in RTCI input

PAL: BS = 33 (21H); default after reset

NTSC: BS = 25 (19H)

PAL: BE = 29 (1DH); default after reset

NTSC: BE = 29 (1DH)

bit RTCE must be set to logic 1 (see Fig.9)

bit RTCE must be set to logic 1 (see Fig.9)

2002 Oct 11

12

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