XC236X 데이터 시트보기 (PDF) - Infineon Technologies
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XC236X Datasheet PDF : 99 Pages
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XC2365
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
97 PORST
I
In/B Power On Reset Input
A low level at this pin resets the XC236x
completely. A spike filter suppresses input pulses
<10 ns. Input pulses >100 ns safely pass the filter.
The minimum duration for a safe recognition
should be 120 ns.
98 ESR1
O0 / I St/B External Service Request 1
EX0AINB
I
St/B External Interrupt Trigger Input
99 ESR0
O0 / I St/B External Service Request 0
Note: After power-up, ESR0 operates as open-
drain bidirectional reset with a weak pull-up.
10 VDDIM
-
PS/M Digital Core Supply Voltage for Domain M
Decouple with a 680 nF ceramic capacitor.
38, VDDI1
64,
88
14 VDDPA
2,
VDDPB
25,
27,
50,
52,
75,
77,
100
-
PS/1 Digital Core Supply Voltage for Domain 1
Decouple each with a 220 nF ceramic capacitor.
All VDDI1 pins must be connected to each other.
-
PS/A Digital Pad Supply Voltage for Domain A
Connect decoupling capacitors to adjacent
VDDP/VSS pin pairs as close as possible to the pins.
Note: The A/D_Converters and ports P5, P6, and
P15 are fed from supply voltage VDDPA.
-
PS/B Digital Pad Supply Voltage for Domain B
Connect decoupling capacitors to adjacent
VDDP/VSS pin pairs as close as possible to the pins.
Note: The on-chip voltage regulators and all ports
except P5, P6, and P15 are fed from supply
voltage VDDPB.
1, VSS
26,
51,
76
-
PS/-- Digital Ground
All VSS pins must be connected to the ground-line
or ground-plane.
1) To generate the reference clock output for bus timing measurement, fSYS must be selected as source for
EXTCLK and P2.8 must be selected as output pin. Also the high-speed clock pad must be enabled. This
configuration is referred to as reference clock output signal CLKOUT.
Data Sheet
26
V0.1, 2007-06
Draft Version
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