SC1182 데이터 시트보기 (PDF) - Semtech Corporation
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SC1182 Datasheet PDF : 14 Pages
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SC1182 & SC1183
POWER MANAGEMENT
Layout Guidelines
Careful attention to layout requirements are necessary for
successful implementation of the SC1182/3 PWM con-
troller. High currents switching at 140kHz are present in
the application and their effect on ground plane voltage
differentials must be understood and minimized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and
position of ground plane interruptions should be such as
to not unnecessarily compromise ground plane integrity.
Isolated or semi-isolated areas of the ground plane may
be deliberately introduced to constrain ground currents to
particular areas, for example the input capacitor and bot-
tom FET ground.
2). The loop formed by the Input Capacitor(s) (Cin), the Top
FET (Q1) and the Bottom FET (Q2) must be kept as small
as possible. This loop contains all the high current, fast
transition switching. Connections should be as wide and
as short as possible to minimize loop inductance. Mini-
mizing this loop area will a) reduce EMI, b) lower ground
injection currents, resulting in electrically cleaner grounds
for the rest of the system and c) minimize source ringing,
resulting in more reliable gate switching signals.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper re-
gion. It should be as short as practical. Since this connec-
tion has fast voltage transitions, keeping this connection
short will minimize EMI. The connection between the out-
put inductor and the sense resistor should be a wide trace
or copper area, there are no fast voltage or current transi-
tions in this connection and length is not so important,
however adding unnecessary impedance will reduce effi-
ciency.
12V IN
5V
10
1 AGND
GATE2 24
2 GATE1
LDOV 23
3 LDOS1
VID0 22
0.1uF
4 LDOS2
5 VCC
VID1 21
VID2 20
6 OVP
VID3 19
0.1uF 7 PWRGOOD
VID4 18
8
CS-
17
VOSENSE
9 CS+
EN 16
10 PGNDH
BSTH 15
11 DH
BSTL 14
12 PGNDL
DL 13
SC1182
Q1
Cin +
1.00k
2.32k
5mOhm
Vout
L
Q2
+
Cout
3.3V
+
Cin Lin
RA1
Q3
RB1
+
Cout Lin1
RA2
Heavy lines indicate
Vo Lin1
high current paths.
For SC1182, RA1, RA2, RB1 and RB2
are not required. LDOS1 connects to
Vo Lin1, LDOS2 connects to Vo Lin2
Q4
RB2
+
Cout Lin2
Vo Lin2
Layout Diagram
SC1182/3
© 2001 Semtech Corp.
7
www.semtech.com
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