SC28L198A1 데이터 시트보기 (PDF) - Philips Electronics
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SC28L198A1 Datasheet PDF : 56 Pages
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Philips Semiconductors
Octal UART for 3.3V and 5V supply voltage
Product specification
SC28L198
Table 3. MR0– Mode Register 0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Bit 7
Bit 6
Bit 5:4
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Xon/Xoff * transparency
Address Recognition *
transparency
TxiNT
0 – flow control characters
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ received are pushed onto
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ the
RxFIFO
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1 – flow control characters
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ received are not pushed
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ onto the RxFIFO
0 – Address characters
received are pushed to
RxFIFO
1 – Address characters
received are not pushed
onto the RxFIFO
TxFIFO
interrupt
level
control
00 – empty
01 – 3/4 empty
10 – 1/2 empty
11 – not full
Bit 3:2
In–band flow control mode
00 – host mode, only the host CPU
may initiate flow control actions
through the CR
01 – Auto Transmitter flow control
10 – Auto Receiver flow control
11 – Auto Receiver and Transmitter
flow control
Bit 1:0
Address Recognition
control
00 – none
01 – Auto wake
10 – Auto doze
11 – Auto wake and
auto doze
* If these bits are not 0 the characters will be stripped regardless of
character when the RxFIFO has loaded to a depth of 12 characters.
bits (3:2) or (1:0)
Draining the RxFIFO to a level of 8 or less causes the Transmitter to
MR0[7:6] – Control the handling of recognized Xon/Xoff or Address
characters. If set, the character codes are placed on the RxFIFO
along with their status bits just as ordinary characters are. If the
emit an Xon character. All transmissions require no host
involvement. A setting other than b’00 in this field precludes the use
of the command register to transmit Xon/Xoff characters.
character is not pushed onto the RxFIFO, its received status will be
lost unless the receiver is operating in the block error mode, see
MR1[5] and the general discussion on receiver error handling.
Interrupt processing is not effected by the setting of these bits. See
Character recognition section.
Note: Interrupt generation in Xon/Xoff processing is controlled by the
IMR (Interrupt Mask Register) of the individual channels. The
interrupt may be cleared by a read of the XISR, the Xon/Xoff
Interrupt Status Register. Receipt of a flow control character will
always generate an interrupt if the IMR is so programmed. The
MR0[5:4] – Controls the fill level at which a transmitter begins to
present its interrupt number to the interrupt arbitration logic. Use of
MR0[3:2] bits have effect on the automatic aspects of flow control
only, not the interrupt generation.
a low fill level minimizes the number of interrupts generated and
maximizes the number of transmit characters per interrupt cycle. It
also increases the probability that the transmitter will go idle for lack
of characters in the TxFIFO.
MR0[1:0] – This field controls the operation of the Address
recognition logic. If the device is not operating in the special or
“wake–up” mode, this hardware may be used as a general purpose
character detector by choosing any combination except b’00.
MR0[3:2] – Controls the Xon/Xoff processing logic. Auto
Interrupt generation is controlled by the channel IMR. The interrupt
Transmitter flow control allows the gating of Transmitter activity by
may be cleared by a read of the XISR, the Xon/Xoff Interrupt Status
Xon/Xoff characters received by the Channel’s receiver. Auto
Register. See further description in the section on the Wake Up
Receiver flow control causes the Transmitter to emit an Xoff
mode.
Table 4. MR1 – Mode Register 1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Bit 7
Bit 6
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxRTS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Control
ISR Read Mode
0 – off
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1 – on
0 – ISR unmasked
1 – ISR masked
Bit 5
Error Mode
0 = Character
1 = Block
Bit 4:3
Parity Mode
00 – With Parity
01 – Force parity
10 – No parity
11 – Special Mode
Bit 2
Parity Type
0 = Even
1 = Odd
Bit 1:0
Bits per Charac-
ter
00 – 5
01 – 6
10 – 7
11 – 8
MR1[7]: Receiver Request to Send Control
This bit controls the deactivation of the RTSN output (I/O2) by the
receiver. This output is asserted and negated by commands applied
via the command register. MR1[7] = 1 causes RTSN to be
automatically negated upon receipt of a valid start bit if the receiver
FIFO is full or greater. RTSN is reasserted when an the FIFO fill
level falls below full. This constitutes a change from previous
members of Philips (Signets)’ UART families where the RTSN
function triggered on FIFO full. This behavior caused problems with
PC UARTs that could not stop transmission at the proper time. .
The RTSN feature can be used to prevent overrun in the receiver, by
using the RTSN output signal, to control the CTSN input of the
transmitting device.
This bit controls the readout mode of the Interrupt Status Register,
ISR. If set, the ISR reads the current status masked by the IMR, i.e.
only interrupt sources enabled in the IMR can ever show a ’1’ in the
ISR. If cleared, the ISR shows the current status of the interrupt
source without regard to the Interrupt Mask setting.
MR1[5]: Error Mode Select
This bit selects the operating mode of the three FIFOed status bits
(FE, PE, received break). In the character mode, status is provided
on a character by character basis; the status applies only to the
character at. the bottom of the FIFO. In the block mode, the status
provided in the SR for these bits is the accumulation (logical OR) of
the status for all characters coming to the top of the FIFO, since the
last reset error command was issued.
MR1[6]: Interrupt Status Masking
MR1[4:3]: Parity Mode Select
1999 Jan 14
19
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