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SC4806MLTRT

Multiple Function Double Ended PWM Controller

Semtech Corporation 

SC4806

POWER MANAGEMENT

Pin Descriptions (Cont.)

Ramp (Pin 6):

GND (Pin 9):

The signal at this pin will be used as the PWM ramp sig-

nal that will be compared to the FB to achieve regula-

tion. The modes of operation can be programmed de-

pending on how this pin is configured (For more details

see Application section).

For voltage mode control, the PWM ramp is generated

via external RC circuit connected from a voltage source

to the Ramp pin. Connection to a fixed voltage source

(REF) will provide a constant peak ramp with a frequency

set by the internal oscillator frequency programed at

the RC pin. Connection to a variable source such as the

VIN will provide the added benefit of the feed forward

function enhancing the converter static and dynamic per-

formance.

For Current mode control the current information from

the ILim pin can be directly connected to the Ramp pin

without the need for the external RC circuit at the Ramp

pin.

If current mode of operation with slope compensation is

required, an external resistor connected from the ILim

pin to the Ramp pin will provide the slope compensa-

tion. The percentage of the slope compensation will be

inversely proportional to the value of the resistor ( the

higher resistor lower slope compensation, the lower re-

sistor higher slope compensation). 1/3 of external feed-

back signal to FB pin by an internal 3 to 1 resistor di-

vider compares to the combined current signal to gener-

ate PWM control signal.

Device power and analog ground. The exposed paddle

area on the back of the package must be connected to

the GND (pin9). Careful attention should be paid to the

layout of the ground planes.

OUTB (Pin 10) and OUTA (Pin 11):

Out of phase gate drive stages. The driver’s peak source

and sink current drive capability of 100mA, enables the

use of an external MOSFET driver or a NPN/PNP transis-

tor totem pole driver.

The oscillator RC network programs the oscillator fre-

quency, which is twice the OUTA/OUTB frequency. To in-

sure that the outputs do not overlap, a dead time can be

generated between the two outputs by sizing the oscilla-

tor timing capacitor (see Application Information section).

VCC (Pin 12):

The supply input for the device. Once VCC has exceeded

the UVLO limit, the internal reference, oscillator, drivers

and logic are powered up. A low ESR capacitor, should

be placed right at the pin to minimize noise problems. It

is recommended that the VCC rising rate during start-up

be smaller than 10V/mS.

THERMAL PAD:

Pad for heatsinking purposes. Connect to ground plane

using multiple thermal vias. Not connected internally.

FB (Pin 7):

The inverting input to the PWM comparator through an

internal 3 to 1 resistor divider. Stray inductances and

parasitic capacitance should be minimized by utilizing

ground planes and correct layout guidelines.

REF (Pin 8):

Bandgap reference output. It is recommended by plac-

ing a minimum 2.2uF low ESR capacitor right at the pin.

 2006 Semtech Corp.

6

www.semtech.com

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