Si3035
Table 10. Switching Characteristics—Serial Interface (DCE = 1, FSD = 1)
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF)
Parameter1,2
Symbol
Min
Typ
Max
Cycle Time, SCLK
tc
354
1/256 Fs
—
SCLK Duty Cycle
tdty
—
50
—
Delay Time, SCLK ↑ to FSYNC ↑
td1
—
—
10
Delay Time, SCLK ↑ to FSYNC ↓
td2
—
—
10
Delay Time, SCLK ↑ to SDO valid
td3
0.25tc – 20
—
0.25tc + 20
Delay Time, SCLK ↑ to SDO Hi-Z
td4
—
—
20
Delay Time, SCLK ↑ to RGDT ↓
td5
—
—
20
Setup Time, SDO Before SCLK ↓
tsu
25
—
—
Hold Time, SDO After SCLK ↓
th
20
—
—
Setup Time, SDI Before SCLK
tsu2
25
—
—
Hold Time, SDI After SCLK
th2
20
—
—
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V.
2. Refer to the section "Multiple Device Support" on page 25 for functional details.
Unit
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
td1
FSYNC
(mode 1)
SDO
(m aster)
SDO
(slave 1)
FSD
SDI
tc
td2
td3
tsu
th
D15
D14
D13
tsu2
D15
th2
D14
D0
D1
D0
Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = 1)
10
Rev. 1.2
td4
td3
D15
td5