MC14LC5540DW 데이터 시트보기 (PDF) - Motorola => Freescale

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MC14LC5540DW

ADPCM Codec

Motorola => Freescale 

handset applications for non–network signaling such as in-

formation services, answering machine control, etc. At the

network interface side of a cordless telephone application,

this function could be used for dialing feedback or call prog-

ress to the handset. The tone generator function is controlled

by the SCP port in BR4, BR5, and BR7. The tone generator

does not work when the device is operated in 64 kbps mode,

except when analog loopback is enabled at BR0 (b5).

POWER–DOWN AND RESET

There are two methods of putting all of this device into a

low power consumption mode that makes the device non-

functional and consumes virtually no power. PDI/RESET is

the power–down input and reset pin which, when taken low,

powers down the device. Another way to power the device

down is by the SCP port at BR0. BR0 allows the analog sec-

tion of this device to be powered down individually and/or the

digital section of this device to be powered down individually.

When the chip is powered down, the VAG, TG, RO, PO+,

PO–, AXO+, AXO–, DT and SCP Tx outputs are high imped-

ance. To return the chip to the power–up state, PDI/RESET

must be high and the SPC clock and the FST or the FSR

frame sync pulses must be present. The ADPCM algorithm is

reset to the CCITT initial state following the reset transition

from low to high logic states. The DT output will remain in a

high–impedance state for at least two FST pulses after pow-

er–up. This device is functional after being reset for full–du-

plex voice coding with the charge pump active.

SIGNAL PROCESSING CLOCK (SPC)

This is the clock that sequences the DSP circuit. This clock

may be asynchronous to all other functions of this device.

Clock frequencies of 20.48 MHz to 24.32 MHz are recom-

mended. This clock is also used to drive a digitally phase–

locked prescaler that is referenced to FST (8 kHz) and

automatically determines the proper divide ratio to use for

achieving the required 256 kHz internal sequencing clock for

all analog signal processing, including analog–to–digital

conversion, digital–to–analog conversion, transmit filtering,

receive filtering and analog gain functions of this device, and

the charge pump. The SPC clock should be a multiple of 256

kHz.

The analog sequencing function of the SPC clock may be

eliminated by reprogramming the device to use the BCLKR

pin as the direct input for the required 256 kHz analog se-

quencing clock. The 256 kHz clock applied at BCLKR must

be an integer 32 times the FST 8 kHz clock and be approxi-

mately rising edge aligned with the FST rising edge. This

mode requires that the transmit and receive ADPCM trans-

fers be controlled by the BCLKT pin. This is reprogrammed

via the SCP port in BR0 (b7).

DIGITAL I/O

The MC14LC5540 is programmable for Mu–Law or A–

Law. The timing for the PCM data transfer is independent of

the companding scheme selected. Table 1 shows the 8–bit

data word format for positive and negative zero and full scale

for both 64 kbps companding schemes (see Figures 1

through 5 for a summary and comparison of the five PCM

data interface modes of this device).

Long Frame Sync

Long Frame Sync is the industry name for one type of

clocking format which controls the transfer of the ADPCM or

PCM data words (see Figures 1 through 4). The “Frame

Sync” or “Enable” is used for two specific synchronizing func-

tions. The first is to synchronize the PCM data word transfer,

and the second is to control the internal analog–to–digital

and digital–to–analog conversions. The term “Sync” refers to

the function of synchronizing the PCM data word onto or off

of the multiplexed serial PCM data bus, also known as a

PCM highway. The term “Long” comes from the duration of

the frame sync measured in PCM data clock cycles. Long

Frame Sync timing occurs when the frame sync is used di-

rectly as the PCM data output driver enable. This results in

the PCM output going low impedance with the rising edge of

the transmit frame sync, and remaining low impedance for

the duration of the transmit frame sync.

The implementation of Long Frame Sync for this device

has maintained industry compatibility and been optimized for

external clocking simplicity. The PCM data output goes low

impedance with the rising edge of the FST pin but the MSB of

the data is clocked out due to the logical AND of the transmit

frame sync (FST pin) with the transmit data clock (BCLKT

pin). This allows either the rising edge of the FST enable or

the rising edge of the BCLKT data clock to be first. This im-

plementation includes the PCM data output remaining low

impedance until the middle of the LSB (seven and a half data

clock cycles for 64 kbps PCM, three and a half data clock

cycles for 32 kbps ADPCM, etc.). This allows the frame sync

to be approximately rising edge aligned with the initiation of

the PCM data word transfer but the frame sync does not

have a precise timing requirement for the end of the PCM

data word transfer. This prevents bus contention between

similar devices on a common bus. The device recognizes

Long Frame Sync clocking when the frame sync is held high

for two consecutive falling edges of the transmit data clock.

In the full–duplex speech mode, the DSP services one en-

code interrupt and one decode interrupt per frame (125 µs).

The encode algorithm (i.e., 16 kbps, 24 kbps, or 32 kbps

ADPCM or 64 kbps PCM) is determined by the length of the

transmit output enable at the FST pin. The length of the FST

enable measured in transmit data clock (BCLKT) cycles tells

the device which encoding rate to use. This enable length in-

formation is used by the encoder each frame. The transmit

ADPCM word corresponding to this request will be computed

during the next frame and be available a total of two frames

after being requested. This transmit enable length informa-

tion can be delayed by the device an additional four frames

corresponding to a total of six frames. This six frames of

delay allows the device to be clocked with the same clocks

for both transmit (encode) and receive (decode), and to be

frame aligned for applications that require every sixth frame

signaling. It is important to note that the enable length in-

formation is delayed and not the actual ADPCM (PCM) sam-

ple word. The amount of delay for the FST enable length is

controlled by the SCP port at BR7 (b5). The digital data out-

put circuitry counts BCLKT cycles to keep the data output

(DT pin) low impedance for the duration of the ADPCM data

word (2, 3, 4, or 8 BCLKT cycles) minus one half of a BCLKT

cycle.

MOTOROLA

MC14LC5540

13

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