ACE1001 데이터 시트보기 (PDF) - Fairchild Semiconductor

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ACE1001

Arithmetic Controller Engine (ACEx™) for Low Power Applications

Fairchild Semiconductor 

4.0 Arithmetic Controller Core

The ACEx microcontroller core is specifically designed for low

cost applications involving bit manipulation, shifting and arith-

metic operations. It is based on a modified Harvard architecture

meaning peripheral, I/O, and RAM locations are addressed sepa-

rately from instruction data.

The core differs from the traditional Harvard architecture by

aligning the data and instruction memory sequentially. This allows

the X-pointer (11-bits) to point to any memory location in either

segment of the memory map. This modification improves the

overall code efficiency of the core and takes advantage of the

flexibility found on Von Neumann style machines.

4.1 CPU Registers

The ACEx microcontroller has five general-purpose registers.

These registers are the Accumulator (A), X-Pointer (X), Program

Counter (PC), Stack Pointer (SP), and Status Register (SR). The

X, SP, and SR registers are all memory-mapped.

Figure 11: Programming Model

A

7

0 8-bit accumulator register

X 10

0 11-bit X pointer register

PC 9

0 10-bit program counter

SP

3 0 4-bit stack pointer

SR

R 0 0 G Z C H N 8-bit status register

NEGATIVE flag

HALF CARRY flag (from bit 3)

CARRY flag (from MSB)

ZERO flag

GLOBAL Interrupt Mask

READY flag (from EEPROM)

12

ACE1001 Product Family Rev. B.1

www.fairchildsemi.com

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