UDA1342TS 데이터 시트보기 (PDF) - Philips Electronics

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UDA1342TS

Audio CODEC

Philips Electronics 

Philips Semiconductors

Audio CODEC

Preliminary specification

UDA1342TS

8.16 I2C-bus interface

Besides the L3-bus mode the UDA1342TS supports the

I2C-bus mode; all the features can be controlled by the

microcontroller with the same register addresses as used

in the L3-bus mode.

The exchange of data and control information between the

microcontroller and the UDA1342TS in the I2C-bus mode

is accomplished through a serial hardware interface

comprising the following pins and signals:

• L3CLOCK: Serial Clock Line (SCL)

• L3DATA: Serial Data line (SDA).

The clock and data timing of the I2C-bus transfer is shown

in Fig.15.

8.16.3 REGISTER ADDRESS

The UDA1342TS register address format is given in

Table 16.

Table 16 I2C-bus register address format

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

0 A6 A5 A4 A3 A2 A1 A0

The register mapping of the I2C-bus and L3-bus interfaces

is the same (see Section 9).

8.16.1 ADDRESSING

Before any data is transmitted on the I2C-bus, the device

which should respond is addressed first. The addressing is

always done with the first byte transmitted after the START

procedure (S).

8.16.2 SLAVE ADDRESS

The UDA1342TS acts as a slave receiver or a slave

transmitter. Therefore, the clock signal SCL is only an

input signal. The data signal SDA is an input or output

signal (bidirectional line).

The UDA1342TS slave address format is shown in

Table 15.

Table 15 I2C-bus slave address format

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

0

0

1

1

0

1 IPSEL R/W

The slave address bit IPSEL corresponds to the hardware

address pin IPSEL which allows selecting the slave

address.

2000 Mar 29

18

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