SP6200EM5-2.85 데이터 시트보기 (PDF) - Signal Processing Technologies
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SP6200EM5-2.85 Datasheet PDF : 17 Pages
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Top View
D
D/2
E/2
E
PACKAGE: 8 PIN DFN
Bottom View
D2
12
E2
K
L
Pin 1 identifier to be located within this shaded area.
Terminal #1 Index Area (D/2 * E/2)
e
b
Side View
A
A1
A3
2x3 8 Pin DFN
JEDEC mo-229C Dimensions in (mm)
(VCED-2) Variation
Symbol
A
A1
A3
b
D
D2
e
E
E2
K
L
MIN NOM MAX
0.80 0.90 1.00
0
-
0.18
0.02
0.20
0.25
0.05
-
0.30
2.00 BSC
1.50 -
1.75
-
0.50
-
3.00 BSC
1.60
- 1.90
0.20
0.30
-
0.40
-
0.50
Date:5/25/04
SP6200/6201 100/200mA CMOS LDO Regulator
15
2x3 8 Pin DFN
© Copyright 2004 Sipex Corporation
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