SP800L(2004) 데이터 시트보기 (PDF) - Signal Processing Technologies

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SP800L
(Rev.:2004)

Low Power Microprocessor Supervisory with Battery Switch-Over

Signal Processing Technologies 

WDI

WDO

t2

RESET

t3

t1

t1

t1 = RESET Timeout Period

t2 = Normal Watchdog Timeout Period

t3 = Watchdog Timeout Period Immediately After RESET

Figure 20. Watchdog Timeout Period and Reset Active Time

Watchdog Function

The watchdog monitors µP activity via the

Watchdog Input (WDI). If the µP becomes

inactive, RESET and RESET are asserted.

To use the watchdog function, connect WDI to

a bus line or µP I/O line. If WDI remains high

or low for longer than the watchdog timeout pe-

riod (1.6s nominal). WDO, RESET, and RESET

are asserted, indicating a software fault or idle

conditions. Refer to RESET and RESET

Outputs and Watchdog Output sections.

OSCIN

7

X No Connect

8 OSCSEL X No Connect

1.6sec Normal Watchdog Timeout

Internal Oscillator

OSCIN

7

Watchdog Input

A change of logic state (minimum 100ns

duration) at WDI during the watchdog period

will reset the watchdog timer. The watchdog

default timout is 1.6sec.

8 OSCSEL X No Connect

100ms Normal Watchdog Timeout

Internal Oscillator

To disable the watchdog function, leave WDI

floating. An internal resistor network (100kΩ

equivalent impedance at WDI) biases WDI to

approximately 1.6V. Internal comparators

detect this level and disable the watchdog timer.

When Vcc is below the reset threshold, the

watchdog function is disabled and WDI is

disconnected from its internal resistor network,

thus becoming high impedance.

CIN

OSCIN

7

8 OSCSEL

Normal Watchdog Timeout

External Oscillator

=

600 x CIN

47pF

[ms]

Watchdog Output

WDO remains high if there is activity (transition

or pulse) at WDI during the watchdog-timeout

period. The watchdog function is disabled and

WDO is a logic high when VCC is less than the

reset threshold or when WDI is an open circuit.

In watchdog mode, if no transition occurs at

WDI during the watchdog-timeout period,

OSCIN

7

8 OSCSEL

Normal Watchdog Timeout = 1024 Clock Periods

External Clock

Figure 21. Selecting Timeout Periods

Date: 5/25/04

SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2004 Sipex Corporation

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