16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
ADDRESSES
CE#
OE#
WE#
DQ6
TCE
TOEH
TOE
Data Sheet
TWO READ CYCLES
WITH SAME OUTPUTS
TBR
VALID DATA
1274 F09.0
FIGURE 11: TOGGLE BIT TIMING DIAGRAM
ADDRESSES
SIX-BYTE CODE FOR CHIP-ERASE
555
2AA
555
555
2AA
555
TSCE
CE#
OE#
WE#
RY/BY#
DQ15-0
TWP
TBY
XXAA XX55
XX80
XXAA
XX55
XX10
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals
are interchageable as long as minimum timings are met. (See Table 14)
X can be VIL or VIH, but no other value.
FIGURE 12: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
21
TBR
VALID
1274 F10.0
S71274-03-000
11/05