Introduction
STi5267
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
QAM demodulation
● Decodes ITU-T J.83-Annexes A/C and DVB-C bit streams
● High-performance integrated ADC for direct IF architecture in all QAM modes
● Supports 16, 32, 64, 128 and 256 point constellations
● Variable symbol rates
● Front derotator for better low symbol rate performance and relaxed tuner constraints
● Integrated matched filtering
● Robust integrated adaptive pre- and post- high multi-tap equalizer
● On-chip FEC A/C with ability to bypass individual blocks
● Built-in clock management for operation from a flexible 4 MHz to 30 MHz external
reference
● Fast signal acquisition
● ADC for RF signal strength indicator
Interfaces
● I²C serial bus interface:
● Fast, up to 400 kHz slave interface
● Four possible slave addresses
● Flexible and DVB-CI compliant TS output
Processor core
The STi5267 integrates a 450 MHz ST40-300 processor core that features a 32-bit
superscalar RISC CPU and IEEE-754 compliant floating point unit (FPU). The ST40-300
includes two-way, set-associative caches and an interrupt controller with 15 user interrupt
sources and an interrupt expansion port.
External memory interface (EMI)
The EMI is a general-purpose interface for attaching Flash memory and peripherals. The
EMI features are:
● Five banks
● Addressing up to at least 64 Mbytes of NOR Flash
● External bus master support through BUSREQ/BUSGNT signals
● Slave Mode EMI support
● Single level cell (SLC) NAND Flash and boot from SLC NAND Flash
● Serial Flash support
● PCI interface, host and device selected on boot
● ATAPI PIO mode 4
● DVB-CI+
Local memory interface (LMI)
The STi5267 integrates one 16-bit DDR2-DDR1 interface. The interface can run up to
400 MHz when configured in DDR2 mode or up to 250 MHz when in DDR1 mode.
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Doc ID 16950 Rev 1