STP08DP05
10 Detection mode functionality
Detection mode functionality
10.1
Phase one: “entering in detection mode“
From the “normal mode” condition the device can switch to the “error mode” by a logic
sequence on the OE/DM2 and LE/DM1 pins as showed in the following table and diagram:
Table 12. Entering in detection truth table
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
H
L
Figure 17. Entering in detection timing diagram
After these five CLK cycles the device goes into the “error detection mode” and at the 6th
rise front of CLK the SDI data are ready for the sampling.
10.2
Phase two: “error detection“
The eight data bits must be set “1” in order to set ON all the outputs during the detection.
The data are latched by LE/DM1 and after that the outputs are ready for the detection
process. When the micro controller switches the OE/DM2 to LOW, the device drives the
LEDs in order to analyze if an OPEN or SHORT condition has occurred.
DocID13405 Rev 6
17/32
32