STV5342 데이터 시트보기 (PDF) - STMicroelectronics
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STV5342 Datasheet PDF : 20 Pages
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STV5342
8/30 READING
8/30 packet is read at row 23 equivalent address.
R8 register must be programmed with D3, D2,
D0 = 0 and D2 = 1 (8/30 selection).
R9 register must be programmed with 23 (17h).
R10 register value corresponds to the position of
the byte to be read (from 0 to 39).
R11A contents the value of the needed byte.
Table 1 : Row 25 received page control data format
D0
PU0
PT0
MU0
MT0
HU0
HT0
C7
C11 MAG0
0
D1
PU1
PT1
MU1
MT1
HU1
HT1
C8
C12 MAG1
0
D2
PU2
PT2
MU2
MT2
HU2
C5
C9
C13 MAG2
0
D3
PU3
PT3
MU3
C4
HU3
C6
C10
C14
0
0
D4
HAM HAM HAM
HAM HAM HAM HAM
HAM FOUND
0
D5
0
0
0
0
0
0
0
0
0
PBLF
D6
0
0
0
0
0
0
0
0
0
0
D7
0
0
0
0
0
0
0
0
0
0
COLUMN
0
1
2
3
4
5
6
7
8
9
Page number : - MAG = magazine, PU = page units, PT = page tens.
Page sub-code : - MU = minutes units, MT = minutes tens, HU = hours units, HT = hours tens.
PBLF = page being looked for, FOUND = low for page found, HAM = hamming error in byte, C4-14 = control bits.
REGISTER MAP (see Table 2)
Registers R0 to R10 are write only whilst R11A is a
read/write and R11B is a read only register respect
to the microprocessor.
The automatic succession on a byte basis is indi-
cated by the arrows in Table 2.
In the normal operating mode TA, TB and TC
should be set to logic level 0.
After power-up the contents of the registers are as
Table 2 : Register specification
follows : all bits in registers R0 to R11A are cleared
to zero with the exception of bits D0 and D1 in
registers R5 and R6 which are set to logical one.
After power-up all the memory bytes are preset to
hexadecimalvalue 20 H (space) with the exception
of the byte corresponding to row 0 of column 7 of
chapter 0 which is set to the value corresponding
to ”alpha white” hexadecimal value 07 H.
D7
D6
D5
*
*
*
TA
7 + P/
ACQ.
8 BIT
ON/OFF
*
*
*
BKGND
OUT
BKGND
OUT
*
*
*
BKGND
IN
BKGND
IN
ACQ
CCT
A1
*
*
COR
OUT
COR
OUT
STATUS
ROW
BTM/TOP
CURSOR
ON
CONCEAL/
REVEAL
*
*
*
*
*
*
*
*
C5
D4
D3
*
*
8/30
ENABLE
ACQ.
CCT
A0
PRD4
DEW/
FULL
FIELD
TB
PRD3
D2
D1
D0
EVEN
TC
SEL11B
OFF
TCS
T1
T0
↵
ON
START
START
START
↵
COLUMN COLUMN COLUMN
SC2
PRD2
SC1
PRD1
SC0
PRD0
↵
*
COR
*
TEXT
*
TEXT
A1
PON
A0
PON
↵
IN
COR
OUT
TEXT
IN
TEXT
OUT
PON
IN
PON
↵
IN
TOP/
OUT
IN
OUT
IN
↵
SINGLE/ BOX ON BOX ON BOX ON
BOTTOM DOUBLE 24
1-23
0
HEIGHT
*
CLEAR
MEM.
8/30
A1
SELECT
A0
↵
R4
R3
R2
R1
R0
↵
C4
C3
C2
C1
C0
R0 Mode 0
R1 Mode 1
R2 Page request adress
R3 Page request data
R4 Display chapter
R5 Display control (normal)
R6
Display control
(newsflash / subtitle)
R7 Display mode
R8 Active chapter
R9 Active row
R10 Active column
D7
(R/W)
60Hz
D6
( R/W)
0
D5
(R/W)
0
D4
(R/W)
0
* Reserved register bits : must be set to 0
D3
(R/W)
0
D2
(R/W)
0
D1
(R/W)
0
D0
(R/W)
VCS
signal
quality
R11A Active data
R11B Status
13/20
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