STV5345 데이터 시트보기 (PDF) - STMicroelectronics
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STV5345 Datasheet PDF : 25 Pages
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STV5345 - STV5345/H - STV5345/T
REGISTER MAP (see Table 2)
Registers R0 to R10 and R12 are write only whilst
R11A is a read/write and R11B is a read only
register respect to the microprocessor.
The automatic succession on a byte basis is indi-
cated by the arrows in Table 2.
In the normal operating mode TA, TB and TC
should be set to logic level 0.
After power-up the contents of the registers are as
follows : all bits in registers R0 to R12 are cleared
to zero with the exception of bits D0 and D1 in
registers R5 and R6 which are set to logical one.
After power-up all the memory bytes are preset to
hexadecimalvalue 20 H (space) with the exception
of the byte corresponding to row 0 of column 7 of
chapter 0 which is set to the value corresponding
to ”alpha white” hexadecimal value 07 H.
Table 2 : Register specification
D7
D6
D5
*
*
*
TA
7 + P/
ACQ.
8 BIT
ON/OFF
BLOCK
SELECT
A3
*
BANK
SELECT
A2
*
ACQ.
CCT
A1
*
*
BKGND
OUT
BKGND
OUT
*
BKGND
IN
BKGND
IN
*
COR
OUT
COR
OUT
STATUS
ROW
BTM/TOP
*
CURSOR
ON
*
CONCEAL/
REVEAL
*
*
*
D7
(R/W)
60Hz
*
*
D6
( R/W)
0
*
C5
D5
(R/W)
0
*
*
EROD
D4
D3
*
*
GHOST
ROW
ENABLE
ACQ.
CCT
A0
PRD4
DEW/
FULL
FIELD
TB
PRD3
D2
D1
D0
EVEN
TC
SEL11B
OFF
TCS
T1
T0
↵
ON
START
START
START
↵
COLUMN COLUMN COLUMN
SC2
PRD2
SC1
PRD1
SC0
PRD0
↵
*
COR
A3
TEXT
A2
TEXT
A1
PON
A0
PON
↵
IN
COR
OUT
TEXT
IN
TEXT
OUT
PON
IN
PON
↵
IN
TOP/
↵ OUT
IN
OUT
IN
SINGLE/ BOX ON BOX ON BOX ON
BOTTOM DOUBLE 24
1-23
0
HEIGHT
A3
CLEAR A2
MEM.
A1
A0
↵
R4
R3
R2
R1
R0
↵
C4
C3
C2
C1
C0
D4
(R/W)
0
A1
D3
(R/W)
0
A0
D2
(R/W)
0
*
D1
(R/W)
0
*
D0
(R/W)
VCS
signal
quality
*
* Reserved register bits : must be set to 0
R0 Mode 0
R1 Mode 1
R2 Page request adress
R3 Page request data
R4 Display chapter
R5 Display control (normal)
R6
Display control
(newsflash / subtitle)
R7 Display mode
R8 Active chapter
R9 Active row
R10 Active column
R11A Active data
R11B Status
R12 Page request address
REFRESH ON DISPLAY FUNCTION
This function allows independently to fill the mem-
ory using 3 acquisition circuits when the 4th one
refreshes the displayed page.
When EROD (D5 of Reg. 12) is 0, refresh on display
function is not active. Four teletext pages are filled
into memory corresponding to addresses of acqui-
sition registers.
Two blocks of 8 pages are selected with A3 (D7of
Reg. 2)
Upper or lower bank of 4 pages is selected with A2
(D6 of Reg. 2).
Acquisition circuits are selected with A1/A0 (D5/D4
of Reg. 2). This 2 bits also determine the 1KByte of
RAM (the chapter) allocated to each acquisition
circuit.
When EROD = 1, refresh on display function is
active.
3 acquisition circuits store pages as described
above. The 4th one stores data into the current
displayed chapter. The chapter is selected with
addresses A3/A2/A1/A0 (D3/D2/D1/D0 of Reg. 4).
Notice that A1/A0 (D1/D0 of Reg. 4) give the circuit
number to be used to refresh this displayed chap-
ter. That means A1/A0of refresh ondisplay function
(D4/D3 of Reg. 12) have to be written identical to
A1/A0 (D1/D0 of Reg. 4), as A2 of acquisition circuit
(D6 of Reg. 2) has to be identical to A2 of displayed
chapter (D2 of Reg. 4).
15/25
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