T35L6432B 데이터 시트보기 (PDF) - Taiwan Memory Technology

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T35L6432B

64K x 32 SRAM

Taiwan Memory Technology 

tm TE

CH

READ/WRITE TIMING

tK C

CLK

tA D SS

tK H

tA D SH tK L

A D SP

T35L6432B

A D SC

A DD RESS A1

tA S tA H

A2

BW E

B W 1-B W 4

CE

(N O T E 2)

ADV

tC E S tC E H

A3

A4

tW S tW H

A5

A6

OE

D

Q

H ig h -Z

tO E H Z

Q (A 1)

Q (A 2)

tD S tD H

D (A 3)

tO E LZ

tK Q

Q (A 4)

(N O T E 1)

Q (A 4+ 1)

Q (A 4+ 2)

D (A 5)

Q (A 4+ 3)

D (A 6)

B ac k -to -B a ck R E A D s

S in g le W R IT E

BURST READ

B ac k -to -B a ck

W R IT E s

:D o n 't c a r e

:U N D E F IN E D

Note: 1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst

address following A4.

2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is

LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.

3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP , ADSC or

ADV cycle is performed.

4. GW is HIGH.

5. Back-to-back READs may be controlled by either ADSP or ADSC .

Taiwan Memory Technology, Inc. reserves the right P. 14

to change products or specifications without notice.

Publication Date: JUL. 2002

Revision: A

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