T83C5101XXX-TISCV 데이터 시트보기 (PDF) - Atmel Corporation

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T83C5101XXX-TISCV

8-bit Low Pin Count Microcontrollers

Atmel Corporation 

Expanded RAM

(XRAM)

T8xC5101/02

The T8xC5101/02 provide 256 additional Bytes of random access memory (RAM) space

for increased data parameter handling and high level language usage.

The T8xC5101/02 have internal data memory that is mapped into four separate

segments.

The four segments are:

1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly

addressable.

2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable

only.

3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly

addressable only.

4. The expanded RAM bytes are indirectly accessed by MOVX instructions.

As external accesses are not possible on the T8xC5101/02 family, it makes no sense to

have the possibility to disable accesses to XRAM. That’s why, compared to

TS80C51RB2, writing a 1 in AUXR register bit 1 will have no effect, and won’t disable

access to the XRAM.

The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper

128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy

the same address space as the SFR. That means they have the same address, but are

physically separate from SFR space.

When an instruction accesses an internal location above address 7FH, the CPU knows

whether the access is to the upper 128 bytes of data RAM or to SFR space by the

addressing mode used in the instruction.

• Instructions that use direct addressing access SFR space. For example: MOV

0A0H, # data, accesses the SFR at location 0B0H (which is P3).

• Instructions that use indirect addressing access the Upper 128 bytes of data RAM.

For example: MOV @R0, # data where R0 contains 0B0H, accesses the data byte

at address 0B0H, rather than P3 (which address is 0B0H).

• The 256 XRAM bytes can be accessed by indirect addressing, with MOVX

instructions. This part of memory which is physically located on-chip, logically

occupies the first 256 bytes of external data memory.

• The XRAM is indirectly addressed, using the MOVX instruction in combination with

any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will

not affect any ports. A write to external data memory locations higher than FFH

(i.e. 0100H to FFFFH) will have no effect. A read will return an indeterminate value.

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and

upper RAM) internal data memory. The stack may not be located in the XRAM.

12

4233H–8051–02/08

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