T83C5101 데이터 시트보기 (PDF) - Atmel Corporation

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T83C5101

8-bit Low Pin Count Microcontrollers

Atmel Corporation 

T8xC5101/02

T8xC5101/02

Enhanced Features

X2 Feature

Description

In comparison to the original 80C52, the T8xC5101/02 implements some new features,

which are:

• The X2 option.

• The Dual Data Pointer.

• The extended RAM.

• The 4 level interrupt priority system.

• Some enhanced features are also located in the UART and the timer 2.

The T8xC5101/02 core needs only 6 clock periods per machine cycle. This feature

called ”X2” provides the following advantages:

• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

• Save power consumption while keeping same CPU power (oscillator power saving).

• Save power consumption by dividing dynamically operating frequency by 2 in

operating and idle modes.

• Increase CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the

XTAL1 signal and the main clock input of the core (phase generator). This divider may

be disabled by software.

The clock for the whole circuit and peripheral is first divided by two before being used by

the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1

input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic

ratio between 40 to 60%. Figure 1 shows the clock generation block diagram. X2 bit is

validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD

mode. Figure 2 shows the mode switching waveforms.

Figure 1. Clock Generation Diagram

XTAL1

FXTAL

2

XTAL1:2

0

1

FOSC

state machine: 6 clock cycles.

CPU control

X2

CKCON reg

8

4233H–8051–02/08

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