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TC665TEUN

SMBus™ PWM Fan Speed Controllers With Fan Fault Detection

Microchip Technology 

5.0 SERIAL COMMUNICATION

5.1 SMBus 2-Wire Interface

The Serial Clock Input (SCLK) and the bi-directional

data port (SDA) form a 2-wire bi-directional serial port

for communicating with the TC664/TC665. The follow-

ing bus protocols have been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

Accordingly, the following Serial Bus conventions have

been defined.

TABLE 5-1: TC664/TC665 SERIAL BUS

CONVENTIONS

Term

Description

Transmitter

Receiver

The device sending data to the bus.

The device receiving data from the

bus.

Master

Slave

Start

The device which controls the bus: ini-

tiating transfers (START), generating

the clock and terminating transfers

(STOP).

The device addressed by the master.

A unique condition signaling the

beginning of a transfer indicated by

SDA falling (High to Low) while SCLK

is high.

Stop

A unique condition signaling the end

of a transfer indicated by SDA rising

(Low to High) while SCLK is high.

ACK

Busy

NOT Busy

Data Valid

A Receiver acknowledges the receipt

of each byte with this unique condi-

tion. The Receiver pulls SDA low dur-

ing SCLK high of the ACK clock-pulse.

The Master provides the clock pulse

for the ACK cycle.

Communication is not possible

because the bus is in use.

When the bus is idle, both SDA and

SCLK will remain high.

The state of SDA must remain stable

during the high period of SCLK in

order for a data bit to be considered

valid. SDA only changes state while

SCLK is low during normal data trans-

fers. (See START and STOP condi-

tions)

TC664/TC665

5.1.1 DATA TRANSFER

The TC664/TC665 support a bi-directional 2-Wire bus

and data transmission protocol. The serial protocol

sequencing is illustrated in Figure 1-1. Data transfers

are initiated by a start condition (START), followed by a

device address byte and one or more data bytes. The

device address byte includes a Read/Write selection

bit. Each access must be terminated by a Stop Condi-

tion (STOP). A convention call Acknowledge (ACK)

confirms the receipt of each byte. Note that SDA can

only change during periods when SCLK is LOW (SDA

changes while SCLK is HIGH are reserved for Start and

Stop conditions). All bytes are transferred MSB (most

significant bit) first.

5.1.2 MASTER/SLAVE

The device that sends data onto the bus is the transmit-

ter and the device receiving data is the receiver. The

bus is controlled by a master device which generates

the serial clock (SCLK), controls the bus access and

generates the START and STOP conditions. The

TC664/TC665 always work as a slave device. Both

master and slave devices can operate as either trans-

mitter or receiver, but the master device determines

which mode is activated.

5.1.3 START CONDITION (START)

A HIGH to LOW transition of the SDA line while the

clock (SCLK) is HIGH determines a START condition.

All commands must be preceded by a START condi-

tion.

5.1.4 ADDRESS BYTE

Immediately following the Start Condition, the host

must transmit the address byte to the TC664/TC665.

The 7-bit SMBus address for the TC664/TC665 is

0011 011. The 7-bit address transmitted in the serial

bit stream must match for the TC664/TC665 to respond

with an Acknowledge (indicating the TC664/TC665 is

on the bus and ready to accept data). The eighth bit in

the Address Byte is a Read-Write Bit. This bit is a ‘1’ for

a read operation or ‘0’ for a write operation. During the

first phase of any transfer, this bit will be set = 0 to indi-

cate that the command byte is being written.

5.1.5 STOP CONDITION (STOP)

A LOW to HIGH transition of the SDA line while the

clock (SCLK) is HIGH determines a STOP condition.

All operations must be ended with a STOP condition.

5.1.6 DATA VALID

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

 2002-2013 Microchip Technology Inc.

DS21737B-page 15

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