TE28F004BET60 데이터 시트보기 (PDF) - Intel
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TE28F004BET60 Datasheet PDF : 57 Pages
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E
4-MBIT SmartVoltage BOOT BLOCK FAMILY
NOTES:
1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC
Characteristics during read mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify and margining operations.
3. Refer to command definition table for valid AIN. (Table 7)
4. Refer to command definition table for valid DIN. (Table 7)
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1)
6. For boot block program/erase, RP# should be held at VHH or WP# should be held at VIH until operation completes
successfully.
7. Time tPHBR is required for successful locking of the boot block.
8. Sampled, but not 100% tested.
9. See Test Configurations (Figure 22), 2.7V–3.6V and 3.3 ± 0.3V Standard Test component values.
10. See Test Configurations (Figure 22), 5V Standard Test component values.
PRELIMINARY
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