TEA1733MT 데이터 시트보기 (PDF) - NXP Semiconductors.

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TEA1733MT

GreenChip SMPS control IC

NXP Semiconductors. 

NXP Semiconductors

TEA1733MT

GreenChip SMPS control IC

The PROTECT input can be used to create an overvoltage detection and OTP functions.

A small capacitor can be connected to the pin if the protections on this pin are not used.

An internal clamp of 4.1 V (typical) protects this pin from excessive voltages.

7.6 Duty cycle control (CTRL pin)

The output power of the converter is regulated by the CTRL pin. This pin is connected to

an internal 5.4 V supply using an internal 7 kΩ resistor.

The CTRL pin voltage sets the peak current which is measured using the ISENSE pin

(see Section 7.10). At low output power, the switching frequency is also reduced (see

Section 7.12). The maximum duty cycle is limited to 72 % (typical).

After eight consecutive converter strokes at the maximum duty cycle, restart protection is

activated. Typically, this will happen when the mains input supply voltage is removed.

7.7 Slope compensation (CTRL pin)

A slope compensation circuit is integrated in the IC for CCM. Slope compensation

guarantees stable operation for duty cycles greater than 50 %.

7.8 Overpower timer (OPTIMER pin)

If the OPTIMER pin is connected to capacitor C4 (see Figure 3), a temporary overload

situation is allowed. Vctrl(Ipeak) (see Figure 1) is set by pin CTRL. When Vctrl(Ipeak) is above

400 mV, the IIO(OPTIMER) current (11 μA typical) is sourced from the OPTIMER pin. If the

voltage on the OPTIMER pin reaches the Vprot(OPTIMER) voltage (2.5 V typical) the

OverPower Protection (OPP) is triggered (see Figure 5).

When the Vprot(OPTIMER) voltage is reached, the TEA1733MT is latched in the off-state.

If the overload is removed before the Vprot(OPTIMER) voltage is reached, the converter will

continue switching.

IO

VO

VISENSE

VOPTIMER

high load

normal

load

Fig 5. Overpower delay: latched

high load

400 mV

Vprot(OPTIMER)

protection

014aaa968

TEA1733MT

Preliminary data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 4 February 2011

© NXP B.V. 2011. All rights reserved.

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