TTRN012G5 데이터 시트보기 (PDF) - Agere -> LSI Corporation
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TTRN012G5
Agere -> LSI Corporation
TTRN012G5 Datasheet PDF : 22 Pages
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Preliminary Data Sheet
August 2000
TTRN012G5 and TTRN012G7
Clock Synthesizer, 16:1 Data Multiplexer
Timing Characteristics
Transmit Timing
Figure 8 shows the timing relationships between the 155.52 MHz or 166.62 MHz output clock (CK155P/N) and the
155.52 Mbits/s or 166.62 Mbits/s input data (D[15:0]P/N) and the input parity valid check (PARITYP/N). Also
shown is the relationship of the VALIDP/N output signal to CK155P/N; this relationship is true for both the contra-
clocking mode and the clockless transfer mode.
tPERIOD
OUTPUT
CK155P
CK155N
INPUTS
D[15:0]P/N,
PARITYP/N
OUTPUT VALIDP/N
tSU
tHOLD
DATA 1
DATA 2
tDD
VALID 1
Note: TSU and THOLD only apply in contra-clocking mode when CLKMODE = 1.
Figure 8. Transmit Timing Waveform
VALID 2
5-7726(F).hr.2
The 155 MHz or 166 MHz output clock and data signals from Figure 8 are characterized in Table 16.
Table 16. LVPECL Input/Output Pin ac Timing Characteristics
Applicable Symbol
Pins
Parameter
Conditions
Min Typ Max Unit
CK155P/N
— Duty Cycle
tPERIOD 155.52 MHz Clock Period
All signals
differential
40
50
60
%
— 6.43 —
ns
166.62 MHz Clock Period
— 6.00 —
ns
Input Timing
D[15:0]P/N, tSU Setup from Clock Edge to
CLKMODE = 1, All 2.0 —
—
ns
PARITYP/N,
D[15:0]P/N or to
signals differential
CK155P/N
PARITYP/N Edge
tHOLD
Hold from Clock Edge to
D[15:0]P/N or to
PARITYP/N Edge
CLKMODE = 1,
0.5
—
—
ns
All signals
differential
tRISE, Rise, Fall Times:
tFALL
20%—80%
All signals
differential
200 500 800 ps
tSKEW Transition Skew Rise to Fall
–100 0 100 ps
Output Timing
VALIDP/N,
CK155P/N
tDD Time Delay from Clock Edge
to VALIDP/N Edge
All signals
differential
–300 800 1500 ps
tRISE, Rise, Fall Times:
tFALL
20%—80%
200 500 800 ps
tSKEW Transition Skew Rise to Fall
–100 0 100 ps
Lucent Technologies Inc.
19
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