TTRN012G5 데이터 시트보기 (PDF) - Agere -> LSI Corporation

부품명

상세내역

제조사

TTRN012G5

TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer

Agere -> LSI Corporation 

Preliminary Data Sheet

August 2000

TTRN012G5 and TTRN012G7

Clock Synthesizer, 16:1 Data Multiplexer

Pin Information (continued)

Table 1. Pin Descriptions—2.5 Gbits/s and Related Signals

Note: In Table 1, when operating the TTRN012G7 device at the OC-48/STM-16 rate, 2.5 Gbits/s should be inter-

preted as 2.48832 Gbits/s. When operating the TTRN012G7 device at the RS FEC OC-48/STM-16 rate,

2.5 Gbits/s should be interpreted as 2.66606 Gbits/s. (A similar interpretation should be made for 2.5 GHz.)

Pin

Symbol* Type† Level

Name/Description

14

D2G5P

O

CML Data Output (2.5 Gbits/s NRZ). 2.5 Gbits/s differential data

15

D2G5N

output.

27

LBDP

O

CML Loopback Data Output. Additional 2.5 Gbits/s differential data

26

LBDN

output for system loopback.

17

CK2G5P

O

CML Clock Output (2.5 GHz). 2.5 GHz differential clock output.

18

CK2G5N

23

RREF1

I Analog Resistor Reference 1. CML current bias reference resistor.

(See Table 15, page 18 for values.)

22

RREF2

I Analog Resistor Reference 2. CML bias reference resistor. Connect a

1.5 kΩ resistor to VCCD.

21

ENCK2G5

Iu CMOS Enable CK2G5P/N Clock Output.

0 = CK2G5P/N buffer powered off

1 or no connection = CK2G5P/N buffer enabled

30

ENLBDN

Iu CMOS Enable LBDP/N Data Output (Active-Low).

0 = LBDP/N buffer enabled

1 or no connection = LBDP/N buffer powered off

11

INVDATN

Iu CMOS Invert D2G5P/N Data Output (Active-Low).

0 = invert

1 or no connection = noninvert

* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.

† I = input, O = output. Iu indicates an internal pull-up resistor on this pin.

Lucent Technologies Inc.

5

Share Link: