AD9857/PCB(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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AD9857/PCB
(Rev.:Rev0)

CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter

Analog Devices 

AD9857

Single-Tone Mode

A block diagram of the AD9857 operating in the Single-Tone

Mode is shown in Figure 17. In the Single-Tone Mode both the

I and Q data paths are disabled from the 14-bit Parallel Data

Port up to and including the modulator. The PDCLK/FUD

pin is an input and functions as a Frequency Update (FUD)

control signal. This is necessary because the frequency tuning

word is programmed via the asynchronous serial port. The FUD

signal causes the new frequency tuning word to become active.

In Single-Tone Mode, the cosine portion of the DDS serves as

the signal source. The output signal consists of a single frequency

as determined by the tuning word stored in the appropriate control

register, per each profile.

In the Single-Tone Mode, no 14-bit parallel data is applied to the

AD9857. The internal DDS core is used to produce a single fre-

quency signal according to the tuning word. The single-tone signal

then moves toward the output, where the Inverse SINC filter and

the output scaling can be applied. Finally, the digital single-tone

signal is converted to the analog domain by the 14-bit DAC.

AD9857

INVERSE

SINC FILTER

INV

SINC

M

U

X 14

8

14-BIT

DAC

DDS

CORE

CONTROL REGISTERS

TUNING

WORD 32

TIMING & CONTROL

OUTPUT

SCALE

VALUE

DAC_RSET

IOUT

IOUT

POWER-

DOWN

LOGIC

PROFILE

SELECT

LOGIC

M

U

X

CLOCK

MULTIPLIER

(4 – 20 )

MODE

CONTROL

REFCLK

REFCLK

PDCLK/

FUD

RESET

SERIAL

PORT

DIGITAL

POWER-

DOWN

PS1 PS0

Figure 17. Single-Tone Mode

PLL

LOCK

CLOCK

INPUT

MODE

REV. 0

–11–

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