68HC68T1M(2006) 데이터 시트보기 (PDF) - Intersil

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68HC68T1M
(Rev.:2006)

CMOS Serial Real-Time Clock With RAM and Power Sense/Control

Intersil 

Dynamic Electrical Specifications Bus Timing VDD ±10%, VSS = 0VDC, TA = 40°C to 85°C

LIMITS (ALL TYPES)

IDENT. NO

PARAMETER

VDD = 3.3V

MIN

MAX

VDD = 5V

MIN

MAX

1

Chip Enable Setup TimetEVCV

2

Chip Enable After Clock Hold TimetCVEX

3

Clock Width HightWH

4

Clock Width LowtWL

5

Data In to Clock Setup TimetDVCV

7

Clock to Data Propagation DelaytCVDV

8

Chip Disable to Output High ZtEXQZ

11

Output Rise Timetr

12

Output Fall Timetf

A

Data in After Clock Hold TimetCVDX

B

Clock to Data Out ActivetCVQX

C

Clock Recovery TimetREC

200

-

100

-

250

-

125

-

400

-

200

-

400

-

200

-

200

-

100

-

-

200

-

100

-

200

-

100

-

200

-

100

-

200

-

100

200

-

100

-

-

200

-

100

200

-

200

-

UNITS

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

17

FN1547.7

March 17, 2006

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