TU25C128PI-2.7 데이터 시트보기 (PDF) - Turbo IC Inc

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TU25C128PI-2.7

CMOS SPI BUS 128K/256K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 16K/32K X 8 BIT EEPROM

Turbo IC Inc 

Turbo IC, Inc.

25C128/25C256

PRELIMINARY INFORMATION

CMOS SPI BUS

128K/256K ELECTRICALLY ERASABLE PROGRAMMABLE ROM

16K/32K X 8 BIT EEPROM

FEATURES :

• Extended Power Supply Voltage

Single Vcc for Read and Programming

(Vcc = 2.7V to 3.6 V) (Vcc = 4.5V to 5.5V)

• Low Power (Isb = 2µa @ 5.5 V)

• SPI (Serial Peripheral Interface) Bus

• Support Byte Write and Page Write (64 Bytes)

• Automatic 64 Byte Page write Operation (max. 10 ms)

Internal Control Timer

Internal Data Latches for 64 Bytes

• Hardware Data Protection by Write Protect Pin

• High Reliability CMOS Technology with EEPROM Cell

Endurance : 100,000 Cycles

Data Retention : 100 Years

• Support SPI Modes 0 (0,0) and 3 (1,1)

• 2.1 Mhz clock rate

• 8 pin JDEC 300 mil wide PDIP and 8 pin 150 mil wide

SOIC

PIN DESCRIPTION

CS

18

VCC

CS 1 8 VCC

SO

27

HOLD SO 2 7 HOLD

WP

36

SCK

WP 3 6 SCK

GND

45

SI

GND 4 5 SI

8 pin SOIC

8 pin PDIP

DESCRIPTION:

The Turbo IC 25C128/25C256 is a serial 128K/256K

EEPROM fabricated with Turbo’s proprietary, high reliabil-

ity, high performance CMOS technology. It’s 128K/256K of

memory is organized as 16384/32768 x 8 bits. This device

offers a flexible byte write and a faster 64-byte page write. It

also offers significant advantages in low power and low VCC

voltage applications.

The Turbo IC 25C128/25C256 is assembled in either a 8-

pin PDIP or 8-pin SOIC package. Pin #1 is the Chip Select

(CS). Pin #2 is the Serial Output (SO). Pin #3 is Write Pro-

tect (WP). Pin #4 is the ground (Vss). Pin #5 is the Serial

Input (SI). Pin #6 is the serial clock (SCK). Pin #7 is the

Hold Input (HOLD)., and Pin #8 is the power supply (Vcc)

pin.

The Turbo IC 25C128/25C256 uses the Serial Peripheral

Interface (SPI), allowing operation on a three-wire bus. The

Turbo IC 25C128/25C256 has separate data input (SI) and

data output (SO) pins. The serial clock (SCK) pin controls

the data transfer. Access to the device is controlled through

the chip select (CS) input.

The Turbo IC 25C128/25C256 provides the block write in-

hibit feature where the user has the option of inhibiting writes

to 3 different sizes of the memory array. A write protect

(WP) pin is provided to prevent inadvertent writes to the

status register. The Turbo 25C128/25C256 can also be put

on hold during any serial communication by asserting the

hold (HOLD) pin.

PIN DESCRIPTION

CHIP SELECT (CS)

The CS input pin selects the Turbo IC 25C128/

25C256. A high to low transition on CS selects

the Turbo IC 25C128/25C256, and keeping CS

low keeps the device activated. When CS is

brought high, the Turbo IC 25C128/25C256 is de-

selected and the serial output pin (SO) is at high

impedance.

SERIAL DATA OUTPUT (SO)

The serial output pin is a push-pull serial data

output. During read, the data is shifted out onto

SO on the falling edge of the serial clock.

WRITE PROTECT (WP)

The WP input pin controls the status register write

protect feature. For normal read and write op-

erations, the WP pin is held high. When the WP

pin is low and the WPEN bit in the status register

is "1", all write operations to the status register

are inhibited. The WP pin function is blocked

when the WPEN bit is "0". This feature allows a

user to install the Turbo IC 25C128/25C256 into

a system with the WP pin tied to ground and still

be able to program the status register. The WP

pin function will then be enabled when the WPEN

bit is set to "1".

SERIAL DATA INPUT (SI)

The SI input pin accepts all opcodes, addresses,

and write data to be input into the Turbo IC

25C128/25C256. The data is latched on the ris-

ing edge of the serial clock.

SERIAL DATA CLOCK (SCK)

The SCK input pin controls the serial bus timing

of the data transfer that occurs on the serial in-

put pin and the serial output pin.

DATA TRANSFER PAUSE (HOLD)

The HOLD input pin pauses the data transfer,

allowing the host to service higher-priority inter-

rupts. Once the device is selected and serial

communication between the controller and the

device is under way, a high to low transition on

HOLD while SCK is low freezes the serial com-

munication. Transitions on the SI and SCK pins

are ignored, and the SO pin is at high imped-

ance. To resume the serial communication,

HOLD is set high while SCK is low. The serial

sequence restarts from where it had stopped with

no loss of continuity. HOLD should always be

high during normal operation.

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