TU25C128PI-2.7 데이터 시트보기 (PDF) - Turbo IC Inc

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TU25C128PI-2.7

CMOS SPI BUS 128K/256K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 16K/32K X 8 BIT EEPROM

Turbo IC Inc 

Turbo IC, Inc.

25C128/25C256

The contents of the status register can be read by the RDSR

instruction. The write protect enable bit, the block write

protect bit, the write enable status, and the busy status of

the Turbo IC 25C128/25C256 can be found through RDSR. Three bits

of the status register can be altered by the WRSR instruction. The

write protect enable bit can be set to enable the hardware write

protect, and the block write protect bits can be set to control

the number of blocks to be write protected, according to Table 3.

When the status register is being programmed, the RDSR instruction

can be used to check the status of the BSY bit. All the other bits

will read back ones during an internal write cycle.

READ OPERATION

The data in the memory array of the Turbo IC 25C128/25C256

can be read as follows: The master pulls the CS pin of the

Turbo IC 25C128/25C256 low, and issues a READ instruction

to the SI pin, which is loaded into the instruction register.

The two address bytes of the memory location to be read are

sent next, which are loaded into the address counter. The two

most significant bits of the address are don't cares for 25C128

while the first MSB of the address is don't care for the 25C256. The

data byte in the memory is shifted out onto the SO pin on the

falling edge of SCK. After the data byte is shifted out, the address

counter is incremented by one. The next data byte is shifted

out. The sequential read continues for as long as the master

provides the clock and keeps CS low. When the address

counter reaches the highest address, it rolls over to the zero

address (0). The read is terminated by bringing CS high.

WRITE OPERATION

The write data can be written into the memory array of the

selected Turbo IC 25C128/25C256 as follows: The master pulls the

CS pin of the selected Turbo IC 25C128/25C256 low, and issues a

WREN instruction to the SI pin, which is loaded into the instruction

register. Then the master brings CS high to set the WREN latch. The

master pulls the CS pin low, and issues the WRITE instruction to the SI

pin, which is loaded into the instruction register. The two address bytes

of the memory location to be written are sent next, which are loaded

into the address counter. The first most significant bit of the address

is a don't care for the 25C256 and the first two MSBs are don't cares

for the 25C128. The data byte to be written is sent next. The data byte

is stored in a data byte latch. The address counter is incremented by

one after the data byte is shifted in. Up to 64 data bytes can be sent

before a write cycle is necessary. To start the internal write cycle, the

CS must be brought high after the least significant bit (D0) of the last

data byte has been loaded. If CS is brought high at any other time, the

write cycle will not start.

PRELIMINARY INFORMATION

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