83C196KD 데이터 시트보기 (PDF) - Intel
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83C196KD Datasheet PDF : 25 Pages
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8XC196KD 8XC196KD20
8XC196KC TO 8XC196KD DESIGN
CONSIDERATIONS
1 Memory Map The 8XC196KD has 1024 bytes of
RAM SFRs and 32K of OTPROM The extra 512
bytes of RAM reside in locations 0200H to
03FFH and the extra 16 Kbytes of OTPROM re-
side in locations 6000H to 9FFFH On the
87C196KC these locations are always external
so KC code may have to be modified to run on
the KD
2 The vertical window scheme has been extended
to include all on-chip RAM
3 IOC3 1 controls the CLKOUT signal This bit must
be 0 to enable CLKOUT
4 The 87C196KD has a different autoprogramming
algorithm to support 32K of on-chip OTPROM
8XC196KD ERRATA
1 83C196KD can possibly miss interrupts on P0 7
See techbit MC0893
DATA SHEET REVISION HISTORY
This data sheet is valid for devices with a ‘‘D’’ and
‘‘E’’ at the end of the topside tracking number Data
sheets are changed as new device information be-
comes available Verify with your local Intel sales
office that you have the latest version before finaliz-
ing a design or ordering devices
The following are important differences between the
272145-002 and 272145-003 data sheets
1 IIL1 specification (logic 0 input current in reset)
was misnamed It is renamed IIL2
2 TLLYV and TLLGV were removed These specifi-
cations are not necessary for high-speed system
designs
3 An errata with 83C196KD P0 7 EXTINT was add-
ed to the errata section
The following are important differences between the
272145-001 and 272145-002 data sheets
1 Added 20 MHz specifications
2 Added 80-lead SQFP package pinout
3 Changed QFP Package iJA to 56 C W from
42 C W
4 Changed VHYS to 300 mV from 150 mV
5 Changed ICC Typical specification at 16 MHz to
65 mA from 50 mA
6 Changed ICC Maximum specification at 16 MHz
to 75 mA from 70 mA
7 Changed IIDLE Typical specification to 17 mA
from 15 mA
8 Changed IIDLE Maximum specification to 25 mA
from 30 mA
9 Changed IPD Typical specification to 8 mA from
15 mA
10 Added IPD Maximum specification
11 Changed TCLDV Maximum specification to
TOSC b 45 from TOSC b 50
12 Changed TLLAX Minimum specification to
TOSC b 35 from TOSC b 40
13 Changed TCHWH Minimum specification to b5
from b10
14 Changed TRHAX Minimum specification to
TOSC b 25 from TOSC b 30
15 Changed THALAZ Maximum specification to
a15 from a10
16 Changed THALBZ Maximum specification to
a20 from a15
17 Added THAHBV Maximum specification
18 Changed TSAM for 10-bit mode to 1 ms from
3 ms
19 Changed TSAM for 8-bit mode to 1 ms from 2 ms
20 Changed IIH1 test condition to VIN e 2 4V from
5 5V
21 Changed IIH1 maximum specification to a200
mA from a100 mA
22 Removed NMI from list of standard inputs
23 Updated ICC and IIDLE vs frequency graph
24 Updated note under DC EPROM Programming
Characteristics
25 Changed ILI1 maximum specification to b12
mA from b6 mA
25
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