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TZA3044U(1998) 데이터 시트보기 (PDF) - Philips Electronics

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TZA3044U
(Rev.:1998)
Philips
Philips Electronics Philips
TZA3044U Datasheet PDF : 18 Pages
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Philips Semiconductors
1.25 Gbits/s Gigabit Ethernet postamplifiers
Objective specification
TZA3044T; TZA3044U
FEATURES
Pin compatible with the NE/SA5224 and NE/SA5225 but
with extended power supply range and less external
component count
Wideband operation from 1.0 kHz to 1.25 GHz typical
Applicable in 1.25 Gbits/s Gigabit Ethernet receivers
Single supply voltage from 3.0 to 5.5 V
PECL (Positive Emitter Coupled Logic) compatible data
outputs
Programmable input signal level-detection to be
adjusted using a single external resistor
On-chip DC offset compensation without external
capacitor
Fully differential for excellent PSRR.
APPLICATIONS
Digital fibre optic receiver for Gigabit Ethernet
applications
Wideband RF gain block.
GENERAL DESCRIPTION
The TZA3044 is a high gain limiting amplifier that is
designed to process signals from fibre optic preamplifiers
like the TZA3043. It is pin compatible with the NE/SA5224
and NE/SA5225 but with extended power supply range,
and needs less external components. Capable of
operating at 1.25 Gbits/s, the chip has input signal level
detection with a user-programmable threshold. The data
and level-detection status outputs are differential outputs
for optimum noise margin and ease of use.
ORDERING INFORMATION
TYPE
NUMBER
TZA3044T
TZA3044U
PACKAGE
NAME
DESCRIPTION
SO16 plastic small outline package; 16 leads; body width 3.9 mm
naked die die in waffle pack carriers; die dimensions 1.58 × 1.58 mm
VERSION
SOT109-1
BLOCK DIAGRAM
handbook, full pagewidth
TEST
2
(2, 10, 15, 21, 26)
DC-OFFSET
COMPENSATION
4 (7)
DIN
5 (8)
A1
A2
DINQ
25 k
RECTIFIER
RSET
Vref
16 (30)
15 (29) 1 k
BAND GAP
REFERENCE
TZA3044
(24) 13
DOUT
A3
(23) 12
DOUTQ
(16) 8
JAM
(18) 10
ST
A4
(17) 9
STQ
(3, 4, 6, 9) (1, 14)
3
1
(11, 12)
6
(13) (19, 20, 22, 25) (27, 28)
7 11
14
AGND
SUB
VCCA
CF DGND
The numbers in brackets refer to the pad numbers of the naked die version.
VCCD
MGR240
Fig.1 Block diagram.
1998 Jul 07
2

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