UCB1300BE 데이터 시트보기 (PDF) - Philips Electronics

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UCB1300BE

Advanced modem/audio analog front-end

Philips Electronics 

Philips Semiconductors

Advanced modem/audio analog front-end

Preliminary specification

UCB1300

10 BIT ADC

The UCB1300 includes a 10 bit successive approximation analog to digital converter (ADC) with built-in track and hold

circuit and an analog multiplexer to select one of the 4 analog inputs (AD0 - AD3), the 4 touch screen inputs (TSPX,

TSMX, TSPY, TSMY) or the pressure output of the touch screen bias circuit. The ADC is used to read-out the touch

screen inputs and it measures the voltage on the four analog high voltage inputs AD0 - AD3. The analog multiplexer

contains 4 resistive dividers to attenuate the high voltage on the AD0 - AD3 inputs to the ADC input range.

internal reference

track&hold

mux

9 to 1

to control reg 11

adcsync

10 bit ADC

10

ADC start

stop logic

adc start

sync

enable

adc_sync_ena

Fig.13 Block diagram of the 10-bit ADC circuit.

The ADC is controlled completely through the SIB interface, but the UCB1300 contains internal logic to ease the control

of the ADC and to minimize the number of SIB frame read/write actions.

A complete ADC control sequence analog to digital conversion consists of several phases. Firstly the ADC has to be

enabled, secondly the input selector must be set to the proper input, thirdly the ADC conversion has to be started and

finally the ADC result has to be read from register 11.

The ADC is activated by setting ADC_ENA in register 10. The ADC circuit, including the track and hold circuit does not

consume any power as long as this bit is reset. The analog input multiplexer is controlled by ADC_INPUT[n] and the ADC

is actually started with the ADC_START bit. When TSPX and TSMX are in the interrupt mode, the ADC cannot be started,

even to measure AD0-3.

The UCB1300 has two different modes to start the ADC conversion, which are selected by the ADC_SYNC_ENA bit.

The default mode is the non-synchronization mode, in which the conversion is started directly with a 0->1 transition of

ADC_START. Secondly the ADC is started at a rising edge of the signal applied to the ADCSYNC pin if

ADC_SYNC_ENA is set. Activating the ADC while keeping the start logic in the started state (ADC_START = 1) will lead

to unpredictible behavior and the value of the ADC data register will not be meaningfull. Always activate a start sequence

for each aquisition (0 to 1 transition on the internal ADC_START signal).

The internal track and hold circuit requires a certain settling time to track the input signal correctly. This can be ensured

from the software by writing first a SIB frame with the ADC multiplexer setting before the SIB frame with the ADC_START

command is transferred. The UCB1300 ADC start/stop logic will detect whether the ADC input multiplexer is changed in

the same SIB frame as the ADC start command is given. In that case it will delay the actual start of the ADC circuit to

ensure that the track and hold settling time requirements are met. This leads to the following two timing diagrams:

1999 Jul 20

20

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