UDA1345TS 데이터 시트보기 (PDF) - Philips Electronics
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UDA1345TS Datasheet PDF : 28 Pages
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Philips Semiconductors
Economy audio CODEC
Product specification
UDA1345TS
12 AC CHARACTERISTICS (DIGITAL)
VDDD = VDDA = VDDO = 2.7 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ; all voltages referenced to ground
(pins 1, 11, 22 and 27); unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
System clock timing; see Fig.7
Tsys
tCWL
tCWH
tr
tf
system clock cycle
fsys LOW-level pulse width
fsys HIGH-level pulse width
rise time
fall time
fsys = 256fs; note 1
fsys = 384fs; note 1
fsys = 512fs; note 2
fsys < 19.2 MHz
fsys ≥ 19.2 MHz
fsys < 19.2 MHz
fsys ≥ 19.2 MHz
Serial input/output data timing; see Fig.8
tBCK
bit clock period
tBCKH
bit clock HIGH time
tBCKL
bit clock LOW time
tr
rise time
tf
fall time
ts(DATAI)
data input set-up time
th(DATAI)
data input hold time
td(DATAO−BCK) data output delay time (from BCK
falling edge)
td(DATAO−WS)
th(DATAO)
ts(WS)
th(WS)
data output delay time (from WS edge) MSB-justified format
data output hold time
word select set-up time
word select hold time
Address and data transfer mode timing; see Figs 4 and 5
Tcy
tHC
tLC
ts(MA)
th(MA)
ts(MT)
th(MT)
L3CLOCK cycle time
L3CLOCK HIGH period
L3CLOCK LOW period
L3MODE set-up time
L3MODE hold time
L3MODE set-up time
L3MODE hold time
address mode
address mode
data transfer mode
data transfer mode
39
88
26
59
36
44
0.30Tsys −
0.40Tsys −
0.30Tsys −
0.40Tsys −
−
−
−
−
1⁄128fs
−
34
−
34
−
−
−
−
−
20
−
0
−
−
−
−
−
0
−
20
−
10
−
500
−
250
−
250
−
190
−
190
−
190
−
190
−
488
ns
325
ns
244
ns
0.70Tsys ns
0.60Tsys ns
0.70Tsys ns
0.60Tsys ns
20
ns
20
ns
−
ns
−
ns
−
ns
20
ns
20
ns
−
ns
−
ns
80
ns
80
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
2002 May 28
21
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