UPD160061AN-XXX 데이터 시트보기 (PDF) - NEC => Renesas Technology
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UPD160061AN-XXX
NEC => Renesas Technology
UPD160061AN-XXX Datasheet PDF : 18 Pages
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µPD160061A
Timing Requirements (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Clock Pulse Width
PWCLK
2.3 V ≤ VDD1 < 2.7 V
25
2.7 V ≤ VDD1 ≤ 3.6 V
15
Clock Pulse High Period
PWCLK(H) 2.3 V ≤ VDD1 < 2.7 V
6
2.7 V ≤ VDD1 ≤ 3.6 V
4
Clock Pulse Low Period
PWCLK(L) 2.3 V ≤ VDD1 < 2.7 V
6
2.7 V ≤ VDD1 ≤ 3.6 V
4
Data Setup Time
tSETUP1
4
Data Hold Time
tHOLD1
0
Start Pulse Setup Time
tSETUP2
4
Start Pulse Hold Time
tHOLD2
0
POL21, POL22 Setup Time
tSETUP3
4
POL21, POL22 Hold Time
tHOLD3
0
STB Pulse Width
PWSTB
2
Last Data Timing
tLDT
2
STB-CLK Time
tSTB -CLK
STB ↑→ CLK ↑
9
Time Between STB and Start Pulse tSTB-STH
STB ↑ → STHR(STHL) ↑
2
POL-STB Time
tPOL-STB
POL ↑ or ↓ → STB ↑
–5
STB-POL Time
tSTB-POL
STB ↓ → POL ↓ or ↑
6
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
ns
CLK
ns
ns
Data Sheet S16041EJ2V0DS
15
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