UPD16633B 데이터 시트보기 (PDF) - NEC => Renesas Technology
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UPD16633B Datasheet PDF : 20 Pages
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µPD16633B
Electrical Specifications (TA = –10 to +75°C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 10.5 V ± 0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Output Voltage DeviationNote 1
Average Output Voltage
VariationNote 2
Output Voltage Range
Logic Part Dynamic Current
Consumption
Driver Part Dynamic Current
Consumption 1Notes 3, 4
Driver Part Dynamic Current
Consumption 1Notes 3, 4
Symbol
∆VO
∆VAV
Condition
Input data
Input data
VO
Input data
IDD1
VDD1, No loads
IDD21
VDD2 = 10.5 V ± 0.5 V, No loads
IDD22
VDD2 = 13.5 V ± 0.5 V, No loads
MIN.
0.1
TYP.
±5
±10
MAX.
Unit
±20
mV
mV
VDD2 – 0.1
V
1.6
10.0
mA
4.4
8.0
mA
6.4
10.0
mA
Notes 1. The output voltage deviation refers to the voltage difference between adjoining output pins when the
display data is the same (within the chip).
2. The average output voltage variation refers to the average output voltage difference between chips.
The average output voltage refers to the average voltage between chips when the display data is the
same.
3. The STB cycle is defined to be 20 µs at fCLK = 40 MHz. The TYP. values refer to an all black or all white
input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern.
4. Refers to the current consumption per driver when cascades are connected under the assumption of
XGA single-sided mounting (10 units).
Switching Characteristics (TA = –10 to +75°C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 10.5 V ± 0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Start Pulse Delay Time
Driver Output Delay Time 1
Driver Output Delay Time 2
Driver Output Delay Time 3
Driver Output Delay Time 4
Input Capacitance 1
Input Capacitance 2
Symbol
tPLH1
tPLH2
tPLH3
tPHL2
tPHL3
CI1
CI2
Condition
CL = 25 pF
CL = 50 pF, RL = 50 kΩ
CL = 50 pF, RL = 50 kΩ
CL = 50 pF, RL = 50 kΩ
CL = 50 pF, RL = 50 kΩ
STHR (STHL) excluded,
TA = 25°C
STHR (STHL),
TA = 25°C
MIN.
TYP.
10
6.6
10
6.4
9.1
6.4
6.3
MAX.
Unit
15
ns
11
µs
17
µs
11
µs
17
µs
15
pF
15
pF
13
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