UPD16641N 데이터 시트보기 (PDF) - NEC => Renesas Technology
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UPD16641N Datasheet PDF : 20 Pages
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µPD16641
Switching Characteristics (TA = –10 to +75°C, VDD1 = 3.0 to 3.6 V, VDD2 = 3.0 to 3.6 V or 4.5 to 5.5 V, VSS1 = VSS2
= 0 V, tr = tf = 3.0 ns)
Parameter
Start pulse delay time
Start pulse delay time
Driver output delay time 1
Driver output delay time 2
Driver output delay time 1
Driver output delay time 2
Driver output delay time 1
Driver output delay time 2
Driver output delay time 1
Driver output delay time 2
Input capacitance
Input capacitance
Input capacitance
Symbol
Condition
MIN.
TYP.
MAX.
Unit
tPLH1
CL = 15 pF
2.0
17
ns
tPHL1
CL = 15 pF
2.0
17
ns
tPLH21
tPLH31
VDD2 = 3.3 V
VO: 0.1 V → 3.2 V
2 kΩ + 75 pF × 2
6.0
12
µs
8.0
14
µs
tPHL21
VO: 3.2 V → 0.1 V
6.0
10
µs
tPHL31
8.0
12
µs
tPLH22
tPLH32
VDD2 = 5.0 V
VO: 0.1 V → 4.9 V
2 kΩ + 75 pF × 2
6.0
10
µs
8.0
12
µs
tPHL22
VO: 4.9 V → 0.1 V
6.0
8.0
µs
tPHL32
8.0
10
µs
CI1
V0 to V10, TA = 25°C
100
pF
CI2
STHR (L), TA = 25°C
10
15
pF
CI3
STHR (L), other than V0 to V10
TA = 25°C
7.0
10
pF
Timing Requirements (TA = –10 to +75°C, VDD1 = 3.0 to 3.6 V, VDD2 = 3.0 to 3.6 V or 4.5 to 5.5 V, VSS1 = VSS2 = 0 V,
tr = tf = 3.0 ns)
Parameter
Clock pulse width
Clock low period
Clock high period
Data setup time
Data hold time
Start pulse setup time
Start pulse hold time
Start pulse low period
Start pulse rise time
STB setup time
Data invalid period
Final data timing
CLK-STB time
STB-CLK time
Symbol
Condition
PWCLK
PWCLK(L)
PWCLK(H)
tSETUP1
tHOLD1
tSETUP2
tHOLD2
tSPL
tSPR
tSETUP3
tINV
tLDT
tCLK-STB
tSTB-CLK
CLK ↑ → STB ↑ or ↓
STB ↑ or ↓ → CLK ↑
MIN.
TYP.
MAX.
Unit
22
ns
4.0
ns
4.0
ns
2.0
ns
2.0
ns
2.0
ns
2.0
ns
2
CLK
80
CLK
1
CLK
1
CLK
1
CLK
7.0
ns
7.0
ns
12
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