* 1. CPU clock (Φ) cycle time is determined by the
oscillator frequency of the connected resonator,
40
the system clock control register (SCC) and the
32
processor clock control register (PCC). The cycle
30
time tCY characteristics for power supply voltage
VDD when the main system clock is in operation is
6
shown below.
5
2. 2tCY or 128/fXX is set by interrupt mode register
4
(IM0) setting.
3
2
1
µPD75212A
tCY VS VDD
(Main System Clock in Operation)
Operation Guaranteed
Range
0.5
0
1
2
3
4
5
6
Power Supply Voltage VDD [V]
54