W77C58 데이터 시트보기 (PDF) - Winbond

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W77C58

8 BIT MICROCONTROLLER

Winbond 

Preliminary W77C58

Watchdog Control

Bit:

7

6

5

SMOD_1 POR

-

Mnemonic: WDCON

4

3

2

1

0

- WDIF WTRF EWT RWT

Address: D8h

SMOD_1:This bit doubles the Serial Port 1 baud rate in mode 1, 2, and 3 when set to 1.

POR: Power-on reset flag. Hardware will set this flag on a power up condition. This flag can be read

or written by software. A write by software is the only way to clear this bit once it is set.

WDIF: Watchdog Timer Interrupt Flag. If the watchdog interrupt is enabled, hardware will set this bit

to indicate that the watchdog interrupt has occurred. If the interrupt is not enabled, then this

bit indicates that the time-out period has elapsed. This bit must be cleared by software.

WTRF: Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer causes a

reset. Software can read it but must clear it manually. A power-fail reset will also clear the bit.

This bit helps software in determining the cause of a reset. If EWT = 0, the watchdog timer

will have no affect on this bit.

EWT: Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer Reset function.

RWT:

Reset Watchdog Timer. This bit helps in putting the watchdog timer into a know state. It also

helps in resetting the watchdog timer before a time-out occurs. Failing to set the EWT before

time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512 clocks after that a watchdog

timer reset will be generated if EWT is set. This bit is self-clearing by hardware.

The WDCON SFR is set to a 0x0x0xx0b on an external reset. WTRF is set to a 1 on a Watchdog

timer reset, but to a 0 on power on/down resets. WTRF is not altered by an external reset. POR is set

to 1 by a power-on reset. EWT is set to 0 on a Power-on reset and unaffected by other resets.

All the bits in this SFR have unrestricted read access. There POR, EWT, WDIF and RWT bits are

protected by TA register. They require Timed Access procedure to write. The remaining bits have

unrestricted write accesses.

Accumulator

Bit: 7

6

5

4

3

2

1

0

ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0

Mnemonic: ACC

ACC.7-0:The A (or ACC) register is the standard 8052 accumulator.

Address: E0h

- 23 -

Publication Release Date: September 1999

Revision A1

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