WM8734 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM8734 Datasheet PDF : 46 Pages
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WM8734
BCLK
DACLRC/
ADCLRC
DACDAT
ADCDAT
tBCH
tBCL
tBCY
tDS
tDD
tLRH
tDH
tLRSU
Production Data
Figure 5 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
50
ns
BCLK pulse width high
BCLK pulse width low
DACLRC/ADCLRC set-up
time to BCLK rising edge
tBCH
tBCL
tLRSU
20
ns
20
ns
10
ns
DACLRC/ADCLRC hold
tLRH
time from BCLK rising edge
10
ns
DACDAT set-up time to
tDS
BCLK rising edge
10
ns
DACDAT hold time from
tDH
BCLK rising edge
10
ns
ADCDAT propagation delay
tDD
from BCLK falling edge
0
10
ns
w
PD Rev 4.1 November 2006
13
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