X28HC256SI-15(2011) 데이터 시트보기 (PDF) - Intersil

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X28HC256SI-15
(Rev.:2011)

5V, Byte Alterable EEPROM

Intersil 

Page Write Cycle

X28HC256

OE

(NOTE 9)

CE

WE

tWP

tBLC

tWPH

ADDRESS

(NOTE 10)

I/O

LAST BYTE

BYTE 0

BYTE 1

BYTE 2

BYTE n

BYTE n + 1

BYTE n + 2

tWC

*For each successive write within the page write operation, A7 to A15 should be the same or

writes to an unknown address could occur.

NOTES:

9. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch

data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.

10. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the

CE or WE controlled write cycle timing.

DATA Polling Timing Diagram (Note 11)

ADDRESS

An

An

An

CE

WE

tOEH

OE

I/O7

DIN = X

DOUT = X

tWC

tOES

tDW

DOUT = X

13

FN8108.3

September 21, 2011

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