X3100V28I 데이터 시트보기 (PDF) - Intersil
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X3100V28I Datasheet PDF : 41 Pages
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X3100, X3101
Over-charge Protection
The X3100 and X3101 monitor the voltage on each
battery cell (VCELL). If for any cell, VCELL > VOV for a
time exceeding TOV, then the Charge FET will be
switched OFF (OVP/LMON = VCC). The device has
now entered Over-charge protection mode (Figure 3).
The status of the discharge FET (via pin UVP) will
remain unaffected.
While in over-charge protection mode, it is possible to
change the state of the OVPC bit in the control register
such that OVP/LMON = Vss (Charge FET = ON).
Although the OVPC bit in the control register can be
changed, the change will not be seen at pin OVP until
the X3100 or X3101 returns from over-charge protec-
tion mode.
The over-charge detection delay TOV, is varied using a
capacitor (COV) connected between pin OVT and
GND. A typical delay time is shown in Table 10. The
delay TOV that results from a particular capacitance
COV, can be approximated by the following linear
equation:
TOV (s) ≈ 10 x COV (µF).
Table 19. Typical over-charge detection time
Symbol
TOV
COV
0.1µF
Delay
1.0s (Typ)
The device further continues to monitor the battery cell
voltages, and is released from over-charge protection
mode when VCELL< VOVR, for all cells. When the
X3100 or X3101 is released from over-charge protec-
tion mode, the charge FET is automatically switched
ON (OVP/LMON = VSS). When the device returns from
over-charge protection mode, the status of the dis-
charge FET (pin UVP/OCP) remains unaffected.
The value of VOV can be selected from the values
shown in Table 4 by setting bits VOV1, VOV0. These
bits are set by using the WCFIG instruction to write to
the configuration register.
Figure 3. Over-charge Protection Mode—Event Diagram
Normal Operation Mode
VCELL
TOV
OVP/LMON
Over-charge
Protection
Mode
Normal Operation Mode
VOV
VOVR
VCC
VSS
Event
0
1
2
3
14
FN8110.1
January 3, 2008
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