X5043 데이터 시트보기 (PDF) - Intersil

부품명

상세내역

제조사

X5043

CPU Supervisor with 4K SPI EEPROM

Intersil 

X5043, X5045

Power-Up and Power-Down Timing

VCC

VTRIP

0 Volts

tR

RESET (X5043)

tPURST

tPURST

RESET (X5045)

VTRIP

tF

tRPD

RESET Output Timing

SYMBOL

PARAMETER

VTRIP

Reset Trip Point Voltage, (-4.5A)

Reset Trip Point Voltage, (Blank)

Reset Trip Point Voltage, (-2.7A)

Reset Trip Point Voltage, (-2.7)

tPURST

tRPD(6)

tF(6)

tR(6)

VRVALID

Power-up Reset Time Out

VCC Detect to Reset/Output

VCC Fall Time

VCC Rise Time

Reset Valid VCC

NOTE:

6. This parameter is periodically sampled and not 100% tested.

CS/WDI vs. RESET/RESET Timing

CS/WDI

RESET

(5043)

RESET

(5045)

tCST

tWDO

tRST

MIN

TYP

4.5

4.62

4.25

4.38

2.85

2.92

2.55

2.62

100

200

10

0.1

1

tWDO

tRST

MAX

4.75

4.5

3.0

2.7

400

500

UNIT

V

ms

ns

µs

ns

V

RESET/RESET Output Timing

SYMBOL

PARAMETER

tWDO

Watchdog Time Out Period,

WD1 = 1, WD0 = 1 (default)

WD1 = 1, WD0 = 0

WD1 = 0, WD0 = 1

WD1 = 0, WD0 = 0

tCST

CS Pulse Width to Reset the Watchdog

tRST

Reset Time Out

MIN

TYP

MAX

UNIT

OFF

100

200

300

ms

450

600

800

ms

1

1.4

2

sec

400

ns

100

200

400

ms

16

FN8126.1

September 16, 2005

Share Link: