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X5323 데이터 시트보기 (PDF) - Intersil
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X5323
CPU Supervisor with 32Kb SPI EEPROM
Intersil
X5323 Datasheet PDF : 21 Pages
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Serial Input Timing
CS
SCK
SI
t
LEAD
t
SU
t
H
MSB IN
X5323, X5325
t
RI
t
CS
t
LAG
t
FI
LSB IN
SO
High Impedance
Serial Output Timing
Symbol
f
SCK
t
DIS
t
V
t
HO
t
RO(3)
t
FO(3)
Parameter
Clock frequency
Output disable time
Output valid from clock low
Output hold time
Output rise time
Output fall time
2.7-5.5V
Min.
Max.
0
2
250
250
0
100
100
Unit
MHz
ns
ns
ns
ns
ns
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t
WC
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Output Timing
CS
SCK
t
CYC
t
WH
t
LAG
t
V
t
HO
t
WL
t
DIS
SO
MSB Out
MSB–1 Out
LSB Out
SI
ADDR
LSB IN
14
FN8131.1
October 27, 2005
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