HSP50215 데이터 시트보기 (PDF) - Intersil

부품명

상세내역

제조사

HSP50215

Digital UpConverter

Intersil 

Waveforms

WR OR-ED CE

t WRL

t AS

A9-0

t WF

FIFORDY

HSP50215

t WRH

t AH

C15-0

t CS

t CH

FIGURE 17. TIMING RELATIVE TO WR OR WITH CE

t RF

t RF

2.0V

0.8V

FIGURE 18. OUTPUT RISE AND FALL TIMES

REFCLK

CAS(15:0),

SYNCIN

t CP

t CL

t CH

t DS

t DH

SAMPCLK, SYNCOUT,

FIFORDY

OUT(15:0)

t DOC

t DO

NOTE: CASZ, OFM, OE are signals that must remain constant with

respect to REFCLK until the part is reset. In the write mode,

either CE or WR must be clocked while the other is tied low.

In read mode, either CE or RD must be clocked while the oth-

er is tied low. Never tie all three interface signals (CE, RD and

WR) low at the same time.

FIGURE 19. TIMING RELATIVE TO REFCLK

OE

t OE

OUT(15:0)

1.5V

1.7V

1.3V

1.5V

t OD

FIGURE 20. OUTPUT ENABLE/DISABLE

t RL

RD OR’ed CE

A9-0

C15-0

t RDO

t ROD

t ADO

FIGURE 21. TIMING RELATIVE TO READ OR TO CE

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

3-442

Share Link: