XE1202A 데이터 시트보기 (PDF) - Semtech Corporation

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XE1202A

433 MHz / 868 MHz / 915 MHz Low-Power, Integrated UHF Transceiver

Semtech Corporation 

XE1202A TrueRF™

Name

Bits

ADParam_RegBW 5

Byte Address

00111

ADParam_Regfreq 4

00111

ADParam_Regcond 3

00111

ADParam_WBBcond 2

00111

ADParam_Xsel

1

00111

RESERVED

0

00111

Description

Baseband

filter

regulation:

0 -> Enabled

1 -> Disabled

bandwidth

Periodicity of baseband filter

bandwidth regulation:

0 -> only at start-up of the receiver

1 -> every 60 seconds whilst

receiver enabled

Regulation process of the baseband

filter bandwidth according to the

selected bandwidth:

0 -> regulation restarted each time

the bandwidth is changed

1 -> no regulation when

bandwidth is changed

Boosting process of the baseband

filter according to the selected

bandwidth:

0 -> boosting restarted each time

the bandwidth is changed

1 -> no boosting when

bandwidth is changed

Selection of the XOSC load

capacitance mode:

0 -> CLop + C0 = 15 pF

1 -> CLop + C0 = 11 pF (low-current

mode)

RESERVED

Table 15: ADParam configuration register

5.2.5 Pattern register

The pattern register may be used to automatically detect the reception of a user-defined pattern and asserts the

PATTERN signal for one bit duration. In this register, a reference pattern length of 8, 16, 24, or 32 bits (see

ADParam_Psize parameter) may be defined. The first byte of the pattern is always stored at byte address A[4:0] (=

01000). If defined, the second and subsequent byte(s) are stored at address A[4:0] = 01001, and so on.

The MSB of the reference pattern is always bit 7 of the address 01000 and the LSB is bit 0 of address 01000,

01001, 01010, or 01011 if the pattern length is 8, 16, 24, or 32 bits, respectively.

Comparing the demodulated data, the first bit received of the last word (or second, third or fourth from last word,

depending upon the value stored in the ADParam_Psize register) is compared with bit 7 (the MSB) of byte address

01000. The last bit received is compared with bit 0 (the LSB) in the Pattern register.

Name

Pattern

Bits

Byte Address Description

7-0

01000

01001

01010

01011

1st byte of the reference pattern

2nd byte

3rd byte

4th byte

Table 16: Pattern register addresses

© Semtech 2006

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