XRT91L30 데이터 시트보기 (PDF) - Exar Corporation

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XRT91L30

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

Exar Corporation 

XRT91L30

REV. 1.0.1

xr

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

TABLE OF CONTENTS

GENERAL DESCRIPTION .................................................................................................1

APPLICATIONS ...........................................................................................................................................1

FIGURE 1. BLOCK DIAGRAM OF XRT91L30 ...................................................................................................................................... 1

FEATURES ......................................................................................................................................................2

FIGURE 2. 64 QFP PIN OUT OF THE XRT91L30 (TOP VIEW)............................................................................................................ 3

ORDERING INFORMATION.....................................................................................................................3

TABLE OF CONTENTS ............................................................................................................ I

PIN DESCRIPTIONS ..........................................................................................................4

.....................................................................................................................................................................4

HARDWARE CONTROL ....................................................................................................................................4

TRANSMITTER SECTION ..................................................................................................................................7

RECEIVER SECTION........................................................................................................................................9

POWER AND GROUND ..................................................................................................................................10

1.0 FUNCTIONAL DESCRIPTION .............................................................................................................12

1.1 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ......................................................................... 12

1.2 CLOCK INPUT REFERENCE FOR CLOCK MULTIPLIER (SYNTHESIZER) UNIT ...................................... 12

TABLE 1: CMU REFERENCE FREQUENCY OPTIONS (DIFFERENTIAL OR SINGLE-ENDED) ................................................................... 12

1.3 DATA LATENCY ............................................................................................................................................. 12

TABLE 2: DATA INGRESS TO DATA EGRESS LATENCY ....................................................................................................................... 12

2.0 RECEIVE SECTION .............................................................................................................................13

2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 13

FIGURE 3. RECEIVE SERIAL INPUT INTERFACE BLOCK ..................................................................................................................... 13

2.2 RECIEVE SERIAL DATA INPUT TIMING ...................................................................................................... 14

FIGURE 4. RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING DIAGRAM .......................................................................................... 14

TABLE 3: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-12/STM-4 OPERATION) ............................................................. 14

TABLE 4: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-3/STM-1 OPERATION) ............................................................... 14

2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15

TABLE 5: CLOCK DATA RECOVERY UNIT REFERENCE CLOCK SETTINGS ............................................................................................ 15

TABLE 6: CLOCK AND DATA RECOVERY UNIT PERFORMANCE .......................................................................................................... 15

2.3.1 INTERNAL CLOCK AND DATA RECOVERY BYPASS ............................................................................................ 16

FIGURE 5. INTERNAL CLOCK AND DATA RECOVERY BYPASS............................................................................................................ 16

2.4 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 16

FIGURE 6. EXTERNAL LOOP FILTERS .............................................................................................................................................. 16

2.5 LOSS OF SIGNAL .......................................................................................................................................... 16

FIGURE 7. LOS DECLARATION CIRCUIT........................................................................................................................................... 17

2.6 SONET FRAME BOUNDARY DETECTION AND BYTE ALIGNMENT RECOVERY .................................... 17

2.7 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 17

FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF SIPO ........................................................................................................................... 18

2.8 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 18

FIGURE 9. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK ............................................................................................................. 18

2.9 DISABLE PARALLEL RECEIVE DATA OUTPUT UPON LOS ..................................................................... 18

2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 19

FIGURE 10. RECEIVE PARALLEL OUTPUT TIMING ............................................................................................................................ 19

TABLE 7: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-12/STM-4 OPERATION) ......................................................................... 19

TABLE 8: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-3/STM-1 OPERATION) ........................................................................... 19

TABLE 9: PECL AND TTL RECEIVE OUTPUTS TIMING SPECIFICATION .............................................................................................. 20

3.0 TRANSMIT SECTION ..........................................................................................................................21

3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................. 21

FIGURE 11. TRANSMIT PARALLEL INPUT INTERFACE BLOCK............................................................................................................. 21

3.2 TRANSMIT PARALLEL DATA INPUT TIMING .............................................................................................. 22

FIGURE 12. TRANSMIT PARALLEL INPUT TIMING .............................................................................................................................. 22

TABLE 10: TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION)......................................................................... 22

TABLE 11: TRANSMIT PARALLEL DATA INPUT TIMING (STS-3/STM-1 OPERATION)........................................................................... 22

3.3 ALTERNATE TRANSMIT PARALLEL BUS CLOCK INPUT OPTION .......................................................... 23

FIGURE 13. ALTERNATE TRANSMIT PARALLEL INPUT INTERFACE BLOCK (PARALLEL CLOCK INPUT OPTION) ...................................... 23

3.4 ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING ....................................................................... 23

FIGURE 14. ALTERNATE TRANSMIT PARALLEL INPUT TIMING............................................................................................................ 23

TABLE 12: ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING (STS-12/STM-4 OPERATION) ...................................................... 24

TABLE 13: ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING (STS-3/STM-1 OPERATION). ....................................................... 24

I

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