Z80189 데이터 시트보기 (PDF) - Zilog

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Z80189

GENERAL-PURPOSE EMBEDDED CONTROLLERS

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Zilog

PC DMA TIMING DIAGRAMS

PC Clock

Internal

HDRQR

HDRQ

PRELIMINARY

Z80189/Z8L189

GENERAL-PURPOSE EMBEDDED CONTROLLERS

(1)

/AEN

/HDACK

/HWR

2

1

HD [0:7]

Valid

(1) The HDRQ will not fall inactive until it ses the

falling edge of /HWR during the /HDACK cycle.

3

4

5

Figure 28. PC DMA Write: Memory-Read, I/O Write

DMA Bus Cycle on PC AT Bus

PC Clock

Internal

HDRQR

(1)

HDRQ

/AEN

/HDACK

2

1

/HRD

HD [0:7]

Valid

(1) The HDRQ will not fall inactive until it sees the

falling edge of /HRD during the /HDACK cycle.

3

4

6

5

Figure 29. PC DMA Read: I/O-Read, Memory-Write

DMA Bus Cycle on PC AT Bus

26

DS971890301

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